Cypress Semiconductor CY7C1362C Manuel d'utilisateur télécharger pdf

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

CY7C1360C

CY7C1362C

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05540 Rev. *H Revised September 14, 2006

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 166 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply (V

)

• 2.5V/3.3V I/O operation (V

DDQ

)

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

Functional Description

[1]

The CY7C1360C/CY7C1362C SRAM integrates 256K x 36

and 512K x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE

), depth-expansion Chip

Enables (CE

and

[2]

), Burst Control inputs (ADSC, ADSP,

and

ADV

), Write Enables (BW

, and BWE), and Global Write

(GW

). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP

) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the Byte Write control inputs. GW when active

LOW cause

s all bytes to be written.

The CY7C1360C/CY7C1362C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE

is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

0, A1, A

ADDRESS

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSC

DQP

WRITE REGISTER

DQP

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

MODE

CE2

CE3

BWE

PIPELINED

ENABLE

DQs

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

DQP

WRITE DRIVER

OUTPUT

BUFFERS

DQP

WRITE DRIVER

A[1:0]

SLEEP

CONTROL

Logic Block Diagram – CY7C1362C (512K x 18)

1 2 3 4 5 6 ... 30 31

Résumé du contenu

Page 1 - CY7C1362C

9-Mbit (256K x 36/512K x 18) Pipelined SRAMCY7C1360CCY7C1362CCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-9

Page 2

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 10 of 31READ Cycle, Begin Burst External L H L L H L X H L L-H QREAD Cycle, Begin Burst External

Page 3

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 11 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1360C/CY7C1362C incorporates a serial boun

Page 4

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 12 of 31TAP Controller Block DiagramPerforming a TAP ResetA RESET is performed by forcing TMS HIG

Page 5 - CY7C1360C (256K x 36)

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 13 of 31IDCODEThe IDCODE instruction causes a vendor-specific, 32-bit codeto be loaded into the i

Page 6

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 14 of 313.3V TAP AC Test ConditionsInput pulse levels ...

Page 7

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 15 of 31VOL2Output LOW Voltage IOL = 100 µA VDDQ = 3.3V 0.2 VVDDQ = 2.5V 0.2 VVIHInput HIGH Volta

Page 8

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 16 of 31165-ball FBGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18)Bit# ball I

Page 9

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 17 of 31119-ball BGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18)Bit# ball IDS

Page 10

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 18 of 31Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not te

Page 11

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 19 of 31Capacitance[16]Parameter Description Test Conditions100 TQFPMax.119 BGAMax.165 FBGAMax. U

Page 12

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 2 of 31.Selection Guide250 MHz 200 MHz 166 MHz UnitMaximum Access Time 2.8 3.0 3.5 nsMaximum Oper

Page 13

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 20 of 31Switching Characteristics Over the Operating Range[17, 18]Parameter Description–250 –200

Page 14

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 21 of 31Switching WaveformsRead Cycle Timing[23]Note: 23. On this diagram, when CE is LOW: CE1 is

Page 15

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 22 of 31Write Cycle Timing[23, 24]Note: 24.Full width Write can be initiated by either GW LOW; or

Page 16

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 23 of 31Read/Write Cycle Timing[23, 25, 26]Notes: 25. The data bus (Q) remains in high-Z followin

Page 17

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 24 of 31ZZ Mode Timing[27, 28]Notes: 27. Device must be deselected when entering ZZ mode. See Cyc

Page 18

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 25 of 31Ordering InformationNot all of the speed, package and temperature ranges are available. P

Page 19

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 26 of 31200 CY7C1360C-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3

Page 20

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 27 of 31250 CY7C1360C-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3

Page 21

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 28 of 31Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INCLUDE MO

Page 22

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 29 of 31Package Diagrams (continued)1.2720.322165437LEABDCHGFKJUPNMTR12.0019.5030° TYP.2.40 MAX.

Page 23

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 3 of 31Pin Configurations AAAAA1A0NC/72MNC/36MVSSVDDNC/18MAAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBDQBDQBV

Page 24

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 30 of 31© Cypress Semiconductor Corporation, 2006. The information contained herein is subject t

Page 25

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 31 of 31Document History PageDocument Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pip

Page 26

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 4 of 31Pin Configurations (continued)AAAAA1A0NC/72MNC/36MVSSVDDNC/18MNCAAAAAAADQPBDQBDQBVDDQVSSQ

Page 27

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 5 of 31Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/144MDQPCDQCDQDDQCDQDA

Page 28

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 6 of 31Pin Configurations (continued)165-Ball FBGA Pinout (3 Chip Enable with JTAG)CY7C1360C (25

Page 29

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 7 of 31Pin Definitions Name I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to sele

Page 30

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 8 of 31Functional OverviewAll synchronous inputs pass through input registers controlledby the ri

Page 31

CY7C1360CCY7C1362CDocument #: 38-05540 Rev. *H Page 9 of 31conducted, the data presented to the DQs is written into thecorresponding address location

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Cypress Semiconductor CY7C1362C Manuel d'utilisateur

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