Cypress Semiconductor enCoRe CY7C6435x Spécifications

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CY7C6431x
CY7C6434x
CY7C6435x
enCoRe™ V Full Speed USB Controller
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-12394 Rev. *R Revised November 20, 2013
enCoRe™ V Full Speed USB Controller
Features
Powerful Harvard-architecture processor
M8C processor speeds running up to 24 MHz
Low power at high processing speeds
Interrupt controller
3.0 V to 5.5 V operating voltage without USB
Operating voltage with USB enabled:
3.15 V to 3.45 V when supply voltage is around 3.3 V
4.35 V to 5.25 V when supply voltage is around 5.0 V
Commercial temperature range:C to +7C
Industrial temperature range: –40 °C to +85 °C
Flexible on-chip memory
Up to 32 KB flash program storage:
50,000 erase and write cycles
Flexible protection modes
Up to 2048 bytes SRAM data storage
In-system serial programming (ISSP)
Complete development tools
Free development tool PSoC Designer™
Full-featured, in-circuit emulator and programmer
Full-speed emulation
Complex breakpoint structure
128-KB trace memory
Precision, programmable clocking
Crystal-less oscillator with support for an external crystal or
resonator
Internal ±5.0% 6, 12, or 24 MHz main oscillator (IMO):
0.25% accuracy with oscillator lock to USB data, no
external components required
Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep. The frequency range is 19 to 50 kHz with a
32-kHz typical value
Programmable pin configurations
Up to 36 general purpose I/O (GPIO) depending on package.
25 mA sink current on all GPIO
60mA total sink current on Even port pins and 60 mA total
sink current on Odd port pins
120 mA total sink current on all GPIOs
Pull-up, High Z, open drain, CMOS drive modes on all GPIO
CMOS drive mode A -5 mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
20 mA total source current on all GPIOs
Low dropout voltage regulator for Port 1 pins:
Programmable to output 3.0, 2.5, or 1.8 V
Selectable, regulated digital I/O on Port 1
Configurable input threshold for Port 1
Hot-swappable Capability on Port 1
Full-Speed USB (12 Mbps)
Eight unidirectional endpoints
One bidirectional control endpoint
USB 2.0-compliant: TID# 40000893
Dedicated 512 bytes buffer
No external crystal required
Additional system resources
Configurable communication speeds
I
2
C slave:
Selectable to 50 kHz, 100 kHz, or 400 kHz
Implementation requires no clock stretching
Implementation during sleep modes with less than 100 A
Hardware address detection
SPI master and SPI slave:
Configurable between 46.9 kHz and 12 MHz
Three 16-bit timers
10-bit ADC used to monitor battery voltage or other signals
with external components
Watchdog and sleep timers
Integrated supervisory circuit
System Bus
6/12/24 MHz Internal Main Oscillator
CPU Core
(M8C)
SROM
8K/16K/32K Flash
SYSTEM RESOURCES
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Port 1 Port 0
Sleep and
Watchdog
Full
Speed
USB
Port 3 Port 2
Prog. LDO
SRAM
2048 Bytes
Interrupt
Controller
enCoRe V
CORE
3 16-Bit
Timers
Port 4
ADC
enCoRe V Block Diagram
Errata: For information on silicon errata, see “Errata” on page 35. Details include trigger conditions, devices affected, and proposed workaround.
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Résumé du contenu

Page 1 - CY7C6435x

CY7C6431xCY7C6434xCY7C6435xenCoRe™ V Full Speed USB ControllerCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-9

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 10 of 4032-pin Part PinoutFigure 7. CY7C64343/CY7C64345 32-pin enCoRe V USB Device

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 11 of 4048-pin Part PinoutFigure 8. CY7C64355/CY7C64356 48-pin enCoRe V USB Device

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 12 of 4024 I/OHR P1[4] Digital I/O, optional external clock input (EXTCLK)25 I/OHR

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 13 of 40Register ReferenceThe section discusses the registers of the enCoRe V devi

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 14 of 40 Table 5. Register Map Bank 0 Table: User SpaceName Addr (0, Hex) Access

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 15 of 40 Table 6. Register Map Bank 1 Table: Configuration SpaceName Addr (1, Hex

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 16 of 40Electrical SpecificationsThis section presents the DC and AC electrical sp

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 17 of 40Absolute Maximum RatingsExceeding maximum ratings may shorten the useful l

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 18 of 40DC Electrical CharacteristicsDC Chip Level SpecificationsTab l e 9 lists

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 19 of 40ADC Electrical SpecificationsTable 10. DC Characteristics – USB Interface

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 2 of 40ContentsFunctional Overview ...

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 20 of 40DC General Purpose I/O SpecificationsTab l e 1 2 lists guaranteed maximum

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 21 of 40DC POR and LVD SpecificationsTab l e 1 3 lists guaranteed maximum and min

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 22 of 40AC Electrical CharacteristicsAC Chip Level SpecificationsThe following tab

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 23 of 40AC General Purpose I/O SpecificationsTab l e 1 8 lists guaranteed maximum

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 24 of 40AC Programming SpecificationsTab l e 2 0 lists guaranteed maximum and min

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 25 of 40AC I2C SpecificationsTab l e 2 1 lists guaranteed maximum and minimum spe

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 26 of 40Figure 14. SPI Master Mode 0 and 2 Figure 15. SPI Master Mode 1 and 3 Tabl

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 27 of 40Figure 16. SPI Slave Mode 0 and 2 Table 23. SPI Slave AC SpecificationsSy

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 28 of 40Figure 17. SPI Slave Mode 1 and 3 TCLK_SS1/FSCLKTHIGHTLOWTSCLK_MISOTOUT_HT

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 29 of 40Package DiagramThis section illustrates the packaging specifications for t

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 3 of 40Functional OverviewThe enCoRe V family of devices are designed to replace m

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 30 of 40Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Packag

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 31 of 40Package HandlingSome IC packages require baking before they are soldered o

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 32 of 40Ordering InformationTable 28. Ordering Code - Commercial PartsOrdering Co

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 33 of 40Ordering Code DefinitionsCYMarketing Code: 7C64 = enCoRe Full-Speed USB Co

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 34 of 40Acronyms Document ConventionsUnits of MeasureNumeric NamingHexadecimal num

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 35 of 40ErrataThis section describes the errata for the enCoRe V – CY7C643xx. Deta

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 36 of 40Figure 21. Eye Diagram WORKAROUNDAvoid the trigger condition by using lo

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 37 of 40Document History PageDocument Title: CY7C6431x, CY7C6434x, CY7C6435x, enCo

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 38 of 40*F 2583853 TYJ / PYRS / HMT10/10/08 Converted from Preliminary to FinalAdd

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 39 of 40*K 2874274 KKU / PYRS02/05/10 On page 4, changed the input voltage range f

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 4 of 40Firmware is required to handle various parts of the USBinterface. The SIE i

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Document Number: 001-12394 Rev. *R Revised November 20, 2013 Page 40 of 40PSoC Designer™ is a trademark and PSoC® and CapSense® are registered tradem

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 5 of 40SPI configuration register (SPI_CFG) sets master/slavefunctionality, clock

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 6 of 40Additional System ResourcesSystem resources, some of which have been previo

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 7 of 40Development ToolsPSoC Designer™ is the revolutionary Integrated DesignEnvir

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 8 of 40Designing with PSoC DesignerThe development process for the PSoC device dif

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CY7C6431xCY7C6434xCY7C6435xDocument Number: 001-12394 Rev. *R Page 9 of 40Pin ConfigurationThe enCoRe V USB device is available in a variety of packa

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