Cypress Semiconductor CY7C68013A Manuel d'utilisateur télécharger pdf

EE318 Electronic Design Lab Project Report, EE Dept., IIT Bombay, April 2007

High speed USB interface for digital processor systems

Group No: D11

Chaitanya Rao (04002028) < [email protected] >

Anshul Jhawar (04002025) < [email protected] >

Atit Parikh (04d07001) < [email protected] >

Supervisor: Prof. M. C. Chandorkar

Abstract

This project attempts to provide a high speed USB (480 Mbps) interface for a TMS320VC33

digital processor system. The interface will support user program download and debugging, as

well as data exchange between a host computer and the processor while user programs are being

executed. A TMS320VC33 board with a full speed USB (12 Mbps) interface already been

developed. The EDL project would involve designing the high speed USB circuit using the

Cypress Semiconductor USB IC CY7C68013A, its interface to the processor, and the associated

USB firmware.

1. Introduction

USB has become the industry standard for external peripheral connection with computer.

Older options like parallel port and RS232 for serial connection have become obsolete.

USB allows the flexibility of speed based on application. A minimal speed of 1.5 Mbps

for HID devices, 12 Mbps for basic data transfer (full speed) and 480 Mbps (high speed)

for video applications. The need for real time computation for simulations is

accomplished by the DSP TMS320vc33 but for this data to be transmitted to the

computer a good throughput is necessary on the controller side. The options being

IEEE1394 fire-wire or high-speed USB. Technically fire-wire can give a maximum data

rate of 400 Mbps. Thus the use of high-speed USB is justified.

One of the applications for this project is the implementation of a limited closed loop

control system with ADC and DAC. The control system will be implemented on the DSP.

2. Design Approach

The design required us to make two essential decisions viz.

1) Use of external FIFO for Buffering

2) 56pin or 100 pin controller.

The 56 pin controller multiplexes the port pins with the FIFO data lines and hence has

lesser pins.It also consumes lesser power. The port pins on the cypress controller would

however be unavailable which is acceptable. The 56 pin package was chosen as it is

1 2 3 4 5 6 7 8 9

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Page 1 - 2. Design Approach

EE318 Electronic Design Lab Project Report, EE Dept., IIT Bombay, April 2007 High speed USB interface for digital processor systems Group No: D11

Page 2 - Block Diagram

easily available ad we would save time in acquisition of a 100 pin cotroller. The FIFOs available as free samples are unidirectional and this would re

Page 3

3.2 Interfacing USB controller and DSP chip Figure 2: CPLD connections The Endpoint buffers for the USB controller chip are implemented as FIFO

Page 4 - 4. Software

3.3 Digital Signal Processor TMS320VC33 circuit Six Serial Port pins of the chip, VC33_RESET\, INT3\ and GND pins have been brought out to common p

Page 5

The predefined functions were modified to match with the new design however maintaining the basic structure for compatibility. For the host side prog

Page 6

5. Test procedures ON receiving the board the USB connector was connected and power on the VCC pins of the DSP as well as the Cypress chip were check

Page 7

References [1] EZ-USB FX2 Technical Reference Manual [2] TMS320C3x User’s Guide [3] TMS320VC33 and CY7C68013A Datasheets [4] http://www.cip.phys

Page 8 - Figure 6: CPLD Connections

Figure 5: External Power Supply, TPS7680 (Regulator) and CPLD Power Pins connection Figure 6: CPLD Connections

Page 9

Figure 7: DSP Chip connections

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