Cypress Semiconductor MoBL-USB CY7C68000A Spécifications télécharger pdf (Page 10)

CY7C68000A

Document #: 38-08052 Rev. *H Page 10 of 15

AC Electrical Characteristics

USB 2.0 Transceiver

USB 2.0-compliant in FS and HS modes.

Timing Diagram

HS/FS Interface Timing - 60 MHz

Figure 3. 60 MHz Interface Timing Constraints

Table 3. 60 MHz Interface Timing Constraints Parameters

Parameter Description Min Typ Max Unit Notes

CSU_MIN

Minimum setup time for TXValid 4 ns

CH_MIN

Minimum hold time for TXValid 1 ns

DSU_MIN

Minimum setup time for Data (transmit direction) 4 ns

DH_MIN

Minimum hold time for Data (transmit direction) 1 ns

CCO

Clock to Control out time for TXReady, RXValid,

RXActive and RXError

18ns

CDO

Clock to Data out time (Receive direction) 1 8 ns

TCSU_MIN

TCH_MIN

TDSU_MIN

TDH_MIN

TCDO

TCCO

DataIn

DataOut

Control_Out

Control_In

CLK

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Cypress Semiconductor MoBL-USB CY7C68000A Spécifications Page 10