Cypress Semiconductor enCoRe CY7C64215 Manuel d'utilisateur télécharger pdf (Page 3)

CY7C64215

Document Number: 38-08036 Rev. *E Page 3 of 33

Applications

■ PC HID devices

❐ Mouse (Optomechanical, Optical, Trackball)

❐ Keyboards

❐ Joysticks

■ Gaming

❐ Game Pads

❐ Console Keyboards

■ General Purpose

❐ Barcode Scanners

❐ POS Terminal

❐ Consumer Electronics

❐ Toys

❐ Remote Controls

❐ USB to Serial

enCoRe III Functional Overview

The enCoRe III is based on flexible PSoC architecture and is a

full featured, full speed (12 Mbps) USB part. Configurable

analog, digital, and interconnect circuitry enable a high level of

integration in a host of consumer, and communication applica-

tions.

This architecture enables the user to create customized

peripheral configurations that match the requirements of each

individual application. Additionally, a fast CPU, Flash program

memory, SRAM data memory, and configurable I/O are included

in both 28-pin SSOP and 56-pin QFN packages.

enCoRe III architecture, as illustrated in the “Block Diagram” on

page 1, is comprised of four main areas: enCoRe III Core, Digital

System, Analog System, and System Resources including a full

speed USB port. Configurable global busing enables all the

device resources to combine into a complete custom system.

The enCoRe III CY7C64215 can have up to seven I/O ports that

connect to the global digital and analog interconnects, providing

access to 4 digital blocks and 6 analog blocks.

enCoRe III Core

The enCoRe III Core is a powerful engine that supports a rich

feature set. The core includes a CPU, memory, clocks, and

configurable GPIO (General Purpose I/O).

The M8C CPU core is a powerful processor with speeds up to

24 MHz, providing a four MIPS 8-bit Harvard architecture micro-

processor. The CPU uses an interrupt controller with up to 20

vectors, to simplify programming of real-time embedded events.

Program execution is timed and protected using the included

Sleep and Watch Dog Timers (WDT).

Memory encompasses 16K of Flash for program storage, 1K of

SRAM for data storage, and up to 2K of EEPROM emulated

using the Flash. Program Flash uses four protection levels on

blocks of 64 bytes, enabling customized software IP protection.

enCoRe III incorporates flexible internal clock generators,

including a 24 MHz IMO (internal main oscillator) accurate to 8%

over temperature and voltage as well as an option for an external

clock oscillator. USB operation requires the OSC LOCK bit of the

USB_CR0 register to be set to obtain IMO accuracy to .25%.

The 24 MHz IMO is doubled to 48 MHz for use by the digital

system, if needed. The 48 MHz clock is required to clock the USB

block and must be enabled for communication. A low power 32

kHz ILO (internal low speed oscillator) is provided for the Sleep

Timer and WDT. The clocks, together with programmable clock

dividers (System Resource), provide flexibility to integrate

almost any timing requirement into enCoRe III. In USB systems,

the IMO self-tunes to ±0.25% accuracy for USB communication.

The extended temperature range for the Industrial operating

range (–40°C to +85°C) requires the use of an external clock

oscillator, which is only available on the 56-pin QFN package.

enCoRe III GPIOs provide connection to the CPU, digital and

analog resources of the device. Each pin’s drive mode may be

selected from eight options, enabling great flexibility in external

interfacing. Every pin also has capability to generate a system

interrupt on high level, low level, and change from last read.

The Digital System

The Digital System is composed of four digital enCoRe III blocks.

Each block is an 8-bit resource that is used alone or combined

with other blocks to form 8, 16, 24, and 32-bit peripherals, which

are called user module references.

Figure 1. Digital System Block Diagram

The following digital configurations can be built from the blocks:

■ PWMs, Timers, and Counters (8-bit and 16-bit)

■ UART 8-bit with selectable parity

■ SPI master and slave

■ I

C Master

■ RF Interface: Interface to Cypress CYFI Radio

The digital blocks are connected to any GPIO through a series

of global buses that can route any signal to any pin. The buses

also enable signal multiplexing and performing logic operations.

This configurability frees your designs from the constraints of a

fixed peripheral controller.

DIGITAL SYSTEM

To System Bus

Digital enCoRe III Block Array

To Analog

System

Row Input

Configuration

Row Output

Configuration

8 Row 0

DBB00 DBB01 DCB02 DCB03

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Port 1

Port 0

Port 3

Port 2

Port 5

Port 4

Port 7

[+] Feedback

1 2 3 4 5 6 7 8 ... 32 33

Commentaires sur ces manuels

Pas de commentaire

Cypress Semiconductor enCoRe CY7C64215 Manuel d'utilisateur Page 3

Commentaires sur ces manuels