Cypress Semiconductor enCoRe CY7C64215 Manuel d'utilisateur télécharger pdf (Page 14)

August 17, 2011 Document No. 001-15340 Rev. *A

AN6073

New Instructions in M8C

The larger ROM size in M8C allows for many more instruc-

tions. The additional instructions (new ones not covered in

the previous M8B-equivalent set) are listed in Table 2. These

can be categorized as offering the following capabilities,

listed roughly in descending order of typical usefulness:

1. Bit test/set/clear/toggle operations on I/O registers.

2. New addressing modes, mainly for direct memory opera-

tions (e.g., AND M[k],a) – including operating with imme-

diate values (3-byte instructions).

3. Expanded set of move/swap choices.

4. The LJMP, with the LCALL shown above, are 3-byte au-

tomatically assembled jump/call instructions that allow

movement around the full program memory (up to 64k)

without restrictions.

5. Indirect addressing into RAM with an auto-incrementing

pointer (MVI instructions).

6. Logical operations on the new flag register (including the

AND F,k and OR F,k shown above as EI/DI substitutes).

7. SSC, supervisory system call; for Cypress Microsystems

this allows access to a supervisory ROM for user func-

tions, such as programming the flash memory ROMX,

which indexes a byte of program memory by concatenat-

ing the A and X registers.

8. Ability to directly add an immediate value to the (single)

stack pointer.

B1 JNZ (false) 4 JNZ k 4 B1 0

C0 JC (false) 4 JC k 4 C0 0

C1 JC (true) 5 JC k 5 C1 0

D0 JNC (true) 5 JNC k 5 D0 0

D1 JNC (false) 4 JNC k 4 D1 0

E0 JACC 7 JACC k 7 E0 0

F0 INDEX 14 INDEX k 13 F0 –1

9, 10

Table 1. Instructions Comparison between M8B and M8C (continued)

B Opcode B Instruction B Cycles C Equiv Inst C Cycles C Opcode Δ Cycles Notes

Table 2. New Instructions on M8C

Name Cycles C-Opcode Name Cycles C-Opcode

SWI 15 0 AND IO[k],i 9 41

ADD M[k],A 7 4 AND IO[X+k],i 10 42

ADD M[x+k],A 8 5 OR IO[k],i 9 43

ADD M[k],i 9 6 OR IO[X+k],i 10 44

ADD M[X+k],i 10 7 TST M[k],i 9 45

ADC M[k],A 7 0C XOR IO[X+k],i 10 46

ADC M[X+k],A 8 0D TST M[k],i 8 47

SUB M[X+k],A 10 0F TST IO[k] 8 49

SUB M[k],i 7 14 TST IO[X+k],i 9 4A

SUB M[X+k],i 8 15 SWAP A,M[k] 7 4C

SUB M[k],i 9 16 SWAP X,M[k] 7 4D

SUB M[X+k],i 10 17 SWAP A,SP 5 4E

SBB M[k],A 7 1C MOV X,SP 4 4F

SBB M[X+k],A 8 1D MOV M[k],i 8 55

SBB M[k],i 9 1E MOV M[X+k],i 9 56

SBB M[X+k],i 10 1F MOV X,M[X+k] 7 59

AND M[k],i 9 26 MOV M[k],X 5 5A

AND M[X+k],i 10 27 MOV A,IO[X+k] 7 5E

ROMX 11 28 MOV M[i],M[k] 10 5F

OR M[k],i 9 2E MOV IO[k],i 8 62

OR M[X+k],i 10 2F MOV IO[X+k],i 9 63

XOR M[k],i 9 36 ASL M[k] 7 65

XOR M[X+k],i 10 37 ASL M[X+k] 8 66

1 2 ... 9 10 11 12 13 14 15 16

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