Cypress Semiconductor FX2LP Guide d'installation Page 13

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EZ-USB Development Board Page -9
3. ‘C2 Load’: SW2=ON, SW1=LARGE
A “C2” load provides a method for loading the EZ-USB internal RAM with 8051 firmware
before enumeration. This ‘boot load’ mechanism allows EZ-USB to enumerate as a fully cus-
tom device, since the 8051 code handles enumeration using VID/PID values embedded in the
code.
At power-on, if the EZ-USB chip detects an EEPROM with the hex value ‘C2’ as its first byte,
it continues to load an EZ-USB configuration byte, followed by blocks of 8051 code. The last
byte loaded takes the 8051 out of reset.
This mode usually requires a large EEPROM, such as the 8 Kilobyte 24LC64.
4.5 Interface Connectors
Six 20-pin headers P1-P6 on the EZ-USB Development Board have pins assigned to be compati-
ble with HP (Agilent) logic analyzers, as shown in Table 3. The slight bulge in the middle rows of
the table (pins 9 and 11) indicates the connector key.
The six headers P1-P6 serve three purposes.
They mate with the proto-typing board supplied in the EZ-USB Development Kit.
They allow direct connection of HP (Agilent) Logic Analyzer pods (Agilent P/N 01650-
63203).
They allow general purpose probing by other logic analyzers or oscilloscopes.
Table 3 shows the logic analyzer pod pin designations. The EZ-USB signals on P1-P6 are
arranged to fulfill the following requirements:
NOTE: If an EEPROM is connected to the SCL and SDA lines, but does not contain 0xC0 or
0xC2 as its first byte, the loader reverts to case 1, ‘generic’. In other words, the boot loader
operates as though no EEPROM is connected. Once the 8051 is running, however, it has
full access to any connected EEPROM, since the 8051 I
2
C controller is completely indepen-
dent of the boot load logic.
Table 3. Logic Analyzer Pinout
Agilent 01650-63203 Pod Pins
CLK1 3 4 D15
D14
5 6 D13
D12 7 8 D11
D10 9 10 D9
D8
11 12 D7
D6 13 14 D5
D4 15 16 D3
D2
17 18 D1
D0 19 20 GND
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