Cypress Semiconductor Perform CY7C1380D Spécifications télécharger pdf (Page 17)

Chapter 3: Building the SOPC System 3–5

Specify the SOPC Builder System Components

Preliminary

9. Now you must remove two connections between the cpu and ddr_sdram

components that are created by default. The cpu/instruction_master port

and cpu/data_master port should not be connected to the ddr_sdram/s1

slave port, because the Nios II processor and the DDR SDRAM are in different

clock regions.

To remove these connections, in the Connections column, click on the filled at the

intersection of each pair of relevant signal lines. After you click on a filled dot that

represents a connection, an open dot indicates the two signals are no longer

connected. Figure 3–3 shows the two severed connections, one of which is labeled.

Add a Clock-Crossing Bridge Between the CPU and DDR SDRAM Clock Domains

To enhance the performance of the video frame buffer, the DDR SDRAM memory

runs on a fast clock. Therefore, the Nios II processor and the DDR SDRAM memory

run on different clocks. For optimal performance, your system requires a

clock-domain crossing bridge between these two components. To add an Avalon-MM

clock-crossing bridge component for DDR SDRAM to your system, perform the

following steps:

1. Under System Contents, expand Bridges and Adapters, expand Memory

Mapped, and double-click Avalon-MM Clock Crossing Bridge.

2. Under Slave-to-master FIFO, for FIFO depth, select 64. Figure 3–4 shows the

Avalon-MM Clock Crossing Bridge MegaWizard interface after you perform this

step.

Figure 3–3. Severed Connections Between the ddr_sdram s1 port and the CPU instruction_master and data_master Ports

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Cypress Semiconductor Perform CY7C1380D Spécifications Page 17