Cypress Semiconductor CY7C1365C Manuel d'utilisateur Page 1

PRELIMINARY 256K x 36/256K x 32/512K x 18 Flowthrough SRAM CY7C1361V25CY7C1363V25CY7C1365V25Cypress Semiconductor Corporation• 3901 North First Street

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY10Write Cycle Description[1, 2, 3]Function (1361/1365) GW BWE BWdBWcBWbBWaRead 11XXXXRead 101111Write Byte

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY11IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1361/63 incorporates a serial boundary scan TestAccess Po

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY12SRAM and cannot preload the Input or Output buffers. TheSRAM does not implement the 1149.1 commands EXTE

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY13TAP Controller State DiagramTEST-LOGICRESETTEST-LOGIC/IDLESELECTDR-SCANCAPTURE-DRSHIFT-DREXIT1-DRPAUSE-D

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY14TAP Controller Block Diagram0012..293031Boundary Scan RegisterIdentification Register012...x012Instruct

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY15TAP AC Switching Characteristics Over the Operating Range[6, 7]Parameter Description Min. Max. UnittTCYC

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY16TAP Timing and Test Conditions(a)TDOCL=20pFZ0=50ΩGND1.25VTest ClockTest Mode SelectTCKTMSTest Data-InTDI

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY17Identification Register DefinitionsInstruction Field Value DescriptionRevision Number(31:28)TBD Reserved

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY18Boundary Scan OrderBit #Signal NameBump ID Bit #Signal NameBump ID1 TBD TBD 36 TBD TBD2 TBD TBD 37 TBD T

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY19Maximum Ratings(Above which the useful life may be impaired. For user guide-lines only, not tested.)Stor

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY2Pin ConfigurationsAAAAA1A0DNUDNUVSSVDDDNUAAAAAAAANC,DPbDQbDQbVDDQVSSQDQbDQbDQbDQbVSSQVDDQDQbDQbVSSNCVDDZZ

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY20Capacitance[10]Parameter Description Test Conditions Max. UnitCIN Input Capacitance TA = 25°C, f = 1 MH

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY21Switching Characteristics Over the Operating Range[12, 13, 14]-133 -117 -100 -80Parameter Description Mi

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY22Timing DiagramsWrite Cycle Timing[16, 17]Notes:16. WE is the combination of BWE, BWx, and GW to define a

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY23Read Cycle Timing[16, 18]Note:18. RDx stands for Read Data from Address X.Timing Diagrams (continued)ADS

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY24Timing Diagrams (continued)In/OutAtAHtAS= DON’T CARE= UNDEFINEDWE is the combination of BWE, BWx, and GW

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY25Timing Diagrams (continued)Pipeline Timing tAS= DON’T CARE= UNDEFINEDtCLZtCHZtDOHCLKADDWECE1Data In/OutA

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY26Timing Diagrams (continued)OEThree-StateI/OstEOHZtEOVtEOLZOE Switching Waveforms

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY27Notes:19. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY28Ordering InformationSpeed(MHz) Ordering CodePackageName Package TypeOperatingRange133 CY7C1361V25-133AC

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY29Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A10151-85050-A

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY3Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNCNCNC,DPcDQcDQdDQcDQdAA AAADSP VDDQCE2ADQcVDDQ

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY4Pin Definitions (100-Pin TQFP)Name I/O DescriptionA0A1AInput-SynchronousAddress Inputs used to select one

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY5VSSGround Ground for the core of the device. Should be connected to ground of the system.VDDQI/O Power Su

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY6Pin Definitions (119-Ball BGA)Name I/O DescriptionA0A1AInput-SynchronousAddress Inputs used to select one

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY7Functional DescriptionSingle Read AccessesThis access is initiated when the following conditions are sat-

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY8Burst SequencesThe CY7C1361V25/CY7C1365V25/CY7C1363V25 providesa two-bit wraparound counter, fed by A[1:0

CY7C1361V25CY7C1363V25CY7C1365V25PRELIMINARY9ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min. Max. UnitICCZZSnooze mode st