Cypress Semiconductor CY7C1383D Manuel d'utilisateur Page 1

18-Mbit (512K x 36/1M x 18) Flow-Through SRAMCY7C1381D, CY7C1381FCY7C1383D, CY7C1383FCypress Semiconductor Corporation • 198 Champion Court • San Jos

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 10 of 29Truth Table for Read/Write [4, 9]Function (CY7C1381D/CY7C1381F) GW B

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 11 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1381D/CY7C1383D/CY7C1

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 12 of 29Bypass RegisterTo save time when serially shifting data through regi

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 13 of 29(Q-bus) pins, when the EXTEST is entered as the currentinstruction.

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 14 of 293.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 15 of 29Identification Register DefinitionsInstruction FieldCY7C1381D/CY7C13

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 16 of 29 119-Ball BGA Boundary Scan Order[14, 15] Bit # Ball ID Bit # Ball I

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 17 of 29165-Ball BGA Boundary Scan Order[14, 16] Bit # Ball ID Bit # Ball ID

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 18 of 29Maximum RatingsExceeding the maximum ratings may impair the useful l

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 19 of 29Capacitance [19]Parameter Description Test Conditions100 TQFP Packag

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 2 of 29Logic Block Diagram – CY7C1381D/CY7C1381F [3] (512K x 36)Logic Block

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 20 of 29Switching Characteristics Over the Operating Range[20, 21]Parameter

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 21 of 29Timing Diagrams Read Cycle Timing [26]tCYCtCLCLKtADHtADSADDRESStCHtA

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 22 of 29Write Cycle Timing [26, 27]Timing Diagrams (continued)tCYCtCLCLKtAD

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 23 of 29Read/Write Cycle Timing [26, 28, 29]Timing Diagrams (continued)tCYC

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 24 of 29ZZ Mode Timing [30, 31]Timing Diagrams (continued)tZZISUPPLYCLKZZtZ

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 25 of 29Ordering InformationNot all of the speed, package and temperature ra

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 26 of 29Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 27 of 29Figure 2. 119-ball BGA (14 x 22 x 2.4 mm) (51-85115)Package Diagrams

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 28 of 29© Cypress Semiconductor Corporation, 2006-2007. The information cont

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 29 of 29Document History PageDocument Title: CY7C1381D/CY7C1383D/CY7C1381F/C

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 3 of 29Pin ConfigurationsAAAAA1A0NCNCVSSVDDAAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBD

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 4 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/1

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 5 of 29Pin Configurations (continued)165-Ball FBGA Pinout (3 Chip Enable)CY7

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 6 of 29Pin DefinitionsName IO DescriptionA0, A1, AInput-SynchronousAddress i

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 7 of 29Functional OverviewAll synchronous inputs pass through input register

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 8 of 29deasserted and the IOs must be tri-stated prior to the presen-tation

CY7C1381D, CY7C1381FCY7C1383D, CY7C1383FDocument #: 38-05544 Rev. *F Page 9 of 29Truth Table [4, 5, 6, 7, 8]Cycle DescriptionADDRESS Used CE1CE2CE3ZZ