Cypress Semiconductor CY7C1386FV25 Manuel d'utilisateur télécharger pdf (Page 23)

CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Document Number: 38-05548 Rev. *E Page 23 of 30

Read/Write Cycle Timing

[26, 28, 29]

Switching Waveforms (continued)

CYC

CLK

ADSP

ADH

ADS

ADDRESS

ADSC

CEH

CES

Data Out (Q)

High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READ

Back-to-Back READs

High-Z

Q(A2)Q(A1)

Q(A4)

WEH

WES

Q(A4+3)

OEHZ

OELZ

CLZ

Back-to-Back

WRITEs

BWE, BW

DON’T CARE

UNDEFINED

Notes

28. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP

or ADSC.

29. GW

is HIGH.

[+] Feedback

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 29 30

CY7C1386DV25, CY7C1386FV25 1
CY7C1387DV25, CY7C1387FV25 1
(512K x 36) 2
(1M x 18) 2
Pin Configurations 3
CY7C1387FV25 (1M x 18) 4
CY7C1386FV25 (512K x 36) 4
CY7C1387DV25 (1M x 18) 5
(3 Chip Enable) 5
CY7C1386DV25 (512K x 36) 5

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Cypress Semiconductor CY7C1386FV25 Manuel d'utilisateur Page 23

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