Cypress Semiconductor CYDC256B16 Manuel d'utilisateur télécharger pdf (Page 19)

CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Document #: 001-01638 Rev. *E Page 19 of 26

Write Cycle No.1: R/W Controlled Timing

[41, 42, 43, 44, 45, 46]

Write Cycle No. 2: CE Controlled Timing

[41, 42, 43, 48]

Notes:

43. t

is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

44. If OE

is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t

PWE

or (t

HZWE

+ t

) to allow the I/O drivers to turn off and data to

be placed on the bus for the required t

. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short

as the specified t

PWE

45. To access RAM, CE

= V

, SEM = V

46. To access upper byte, CE

= V

, UB = V

, SEM = V

To access lower byte, CE

= V

, LB = V

, SEM = V

47. Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.

48. During this period, the I/O pins are in the output state, and input signals must not be applied.

Switching Waveforms (continued)

PWE

R/W

DATA OUT

DATA IN

ADDRESS

HZOE

HZWE

LZWE

[47]

[44]

[45, 46]

NOTE 48

SCE

R/W

DATA IN

ADDRESS

[45, 46]

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 25 26

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Cypress Semiconductor CYDC256B16 Manuel d'utilisateur Page 19

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