Cypress Semiconductor CYS25G0101DX-ATC Manuel d'utilisateur télécharger pdf (Page 2)

CYS25G0101DX

Document Number: 38-02009 Rev. *K Page 2 of 17

16

TXD[15:0]

Input

Register

Shifter

TXCLKI

LOCKREF

TX PLL

X16

FIFO

IN

±

OUT

±

÷

16

(155.52 MHz)

LOOPTIME

TX Bit-Clock

REFCLK

±

DIAGLOOP

LINELOOP

LOOPA

16

Output

Register

RXD[15:0]

Shifter

RX CDR

PLL

÷

16

RXCLK

(155.52 MHz)

Recovered

Bit-Clock

Retimed

Data

(155.52 MHz)

Lock-to-Data/

Clock Control

Logic

Lock-to-Ref

LFI

SD

FIFO_ERR TXCLKO

FIFO_RST

RESETPWRDN

Logic Block Diagram

1 2 3 4 5 6 7 ... 16 17

SONET OC-48 Transceiver 1
CYS25G0101DX 10

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