Cypress Semiconductor enCoRe CY7C604XX Manuel d'utilisateur télécharger pdf (Page 23)

CY7C603xx

Document #: 38-16018 Rev. *D Page 23 of 29

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V

and 0°C <

< 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 24.2.7V AC Digital Block Specifications

Function Description Min. Typ. Max. Unit Notes

All Functions Maximum Block Clocking Frequency 12.7 MHz 2.4V < Vdd < 3.0V.

Timer/

Counter/

PWM

Enable Pulse Width 100 – – ns

Maximum Frequency – – 12.7 MHz

Dead Band Kill Pulse Width:

Asynchronous Restart Mode 20 – – ns

Synchronous Restart Mode 100 – – ns

Disable Mode 100 – – ns

Maximum Frequency – – 12.7 MHz

SPIM Maximum Input Clock Frequency – – 6.35 MHz Maximum data rate at 3.17 MHz due

to 2 x over clocking.

SPIS Maximum Input Clock Frequency – – 4.1 MHz

Width of SS_ Negated Between Transmissions 100 – – ns

Transmitter Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz due

to 8 x over clocking.

Receiver Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz due

to 8 x over clocking.

Table 25.3.3V AC External Clock Specifications

Parameter Description Min. Typ. Max. Unit Notes

OSCEXT

Frequency with CPU Clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3V.

With the CPU clock divider set to 1, the external

clock must adhere to the maximum frequency

and duty cycle requirements.

OSCEXT

Frequency with CPU Clock divide by 2 or

greater

0.186 – 24.6 MHz If the frequency of the external clock is greater

than 12 MHz, the CPU clock divider must be

set to 2 or greater. In this case, the CPU clock

divider will ensure that the fifty percent duty

cycle requirement is met.

– High Period with CPU Clock divide by 1 41.7

– 5300 ns

– Low Period with CPU Clock divide by 1 41.7 – –ns

– Power Up IMO to Switch 150

– – Ps

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