Cypress Semiconductor Perform nvSRAM Spécifications télécharger pdf (Page 4)

CY14B256KA

Document Number: 001-55720 Rev. *H Page 4 of 28

Device Operation

The CY14B256KA nvSRAM is made up of two functional

components paired in the same physical cell. These are a SRAM

memory cell and a nonvolatile QuantumTrap cell. The SRAM

memory cell operates as a standard fast static RAM. Data in the

SRAM is transferred to the nonvolatile cell (the STORE

operation), or from the nonvolatile cell to the SRAM (the RECALL

operation). Using this unique architecture, all cells are stored and

recalled in parallel. During the STORE and RECALL operations

SRAM read and write operations are inhibited. The

CY14B256KA supports infinite reads and writes similar to a

typical SRAM. In addition, it provides infinite RECALL operations

from the nonvolatile cells and up to 1 million STORE operations.

Refer the Truth Table For SRAM Operations on page 24 for a

complete description of read and write modes.

SRAM Read

The CY14B256KA performs a read cycle whenever CE and OE

are LOW, and WE and HSB are HIGH. The address specified on

pins A

0–14

determines which of the 32,768 data bytes are

accessed. When the read is initiated by an address transition,

the outputs are valid after a delay of t

(read cycle #1). If the

read is initiated by CE

or OE, the outputs are valid at t

ACE

or at

DOE

, whichever is later (read cycle #2). The data output

repeatedly responds to address changes within the t

access

time without the need for transitions on any control input pins.

This remains valid until another address change or until CE or

is brought HIGH, or WE or HSB is brought LOW.

SRAM Write

A write cycle is performed when CE and WE are LOW and HSB

is HIGH. The address inputs must be stable before entering the

write cycle and must remain stable until CE

or WE goes HIGH at

the end of the cycle. The data on the common I/O pins IO

0–7

are

written into the memory if it is valid t

before the end of a

WE-

controlled write, or before the end of an CE-controlled write.

It is recommended that OE

be kept HIGH during the entire write

cycle to avoid data bus contention on common I/O lines. If OE

left LOW, internal circuitry turns off the output buffers t

HZWE

after

goes LOW.

AutoStore Operation

The CY14B256KA stores data to the nvSRAM using one of three

storage operations. These three operations are: Hardware

STORE, activated by the HSB; Software STORE, activated by

an address sequence; AutoStore, on device power-down. The

AutoStore operation is a unique feature of QuantumTrap

technology and is enabled by default on the CY14B256KA.

During normal operation, the device draws current from V

charge a capacitor connected to the V

CAP

pin. This stored

charge is used by the chip to perform a single STORE operation.

If the voltage on the V

pin drops below V

SWITCH

, the part

automatically disconnects the V

CAP

pin from V

. A STORE

operation is initiated with power provided by the V

CAP

capacitor.

Note If the capacitor is not connected to V

CAP

pin, AutoStore

must be disabled using the soft sequence specified in Preventing

AutoStore on page 6. In case AutoStore is enabled without a

capacitor on V

CAP

pin, the device attempts an AutoStore

operation without sufficient charge to complete the Store. This

corrupts the data stored in nvSRAM.

Figure 2. AutoStore Mode

Figure 2 shows the proper connection of the storage capacitor

CAP

) for automatic STORE operation. Refer to DC Electrical

Characteristics on page 16 for the size of the V

CAP

. The voltage

on the V

CAP

pin is driven to V

by a regulator on the chip. Place

a pull-up on WE

to hold it inactive during power-up. This pull-up

is only effective if the WE

signal is tristate during power-up. Many

MPUs tristate their controls on power-up. This must be verified

when using the pull-up. When the nvSRAM comes out of

power-on-RECALL, the MPU must be active or the WE

held

inactive until the MPU comes out of reset.

To reduce unnecessary nonvolatile stores, AutoStore and

Hardware STORE operations are ignored unless at least one

write operation has taken place since the most recent STORE or

RECALL cycle. Software initiated STORE cycles are performed

regardless of whether a write operation has taken place.

Hardware STORE (HSB) Operation

The CY14B256KA provides the HSB pin to control and

acknowledge the STORE operations. The HSB

pin is used to

request a Hardware STORE cycle. When the HSB

pin is driven

LOW, the CY14B256KA conditionally initiates a STORE

operation after t

DELAY

. An actual STORE cycle begins only if a

write to the SRAM has taken place since the last STORE or

RECALL cycle. The HSB

pin also acts as an open drain driver

(internal 100 k weak pull-up resistor) that is internally driven

LOW to indicate a busy condition when the STORE (initiated by

any means) is in progress.

Note After each Hardware and Software STORE operation HSB

is driven HIGH for a short time (t

HHHD

) with standard output high

current and then remains HIGH by internal 100 k pull-up

resistor.

SRAM write operations that are in progress when HSB

is driven

LOW by any means are given time (t

DELAY

) to complete before

the STORE operation is initiated. However, any SRAM write

cycles requested after HSB

goes LOW are inhibited until HSB

returns HIGH. In case the write latch is not set, HSB is not driven

LOW by the CY14B256KA. But any SRAM read and write cycles

are inhibited until HSB

is returned HIGH by MPU or other

external source.

During any STORE operation, regardless of how it is initiated,

the CY14B256KA continues to drive the HSB

pin LOW, releasing

0.1 uF

10 kOhm

CAP

1 2 3 4 5 6 7 8 9 ... 27 28

Commentaires sur ces manuels

Pas de commentaire

Cypress Semiconductor Perform nvSRAM Spécifications Page 4

Commentaires sur ces manuels

Produits connexes et manuels pour Non Cypress Semiconductor Perform nvSRAM