Cypress Semiconductor Perform CY20x34 Fiche technique télécharger pdf (Page 29)

I2C Bootloader

Document Number: 001-13258 Rev. *J Page 29 of 39

Configuration Registers

This section describes the PSoC Resource Registers used or modified by the BootLdrI2C User Module.

Table 1. Resource I2C_CFG: Bank 0 reg[D6] Configuration Register

Pin Select: Selects either SCL and SDA as P1[5]/P1[7] or P1[0]/P1[1].

Bus Error Interrupt Enable: Enable I

C interrupt generation on a Bus Error.

Stop Error Interrupt Enable: Enable an I

C interrupt on an I

C Stop condition.

Clock Rate[1,0]: Select from 3 valid Clock rates; 50, 100, and 400 Kbps (400 Kbps when CPU_Clk_speed

is greater than 6 MHz).

Enable Master: Enable the I

C HW block as a bus Master.

Enable Slave: Enable the I

C HW block as a bus Slave.

Table 2. Resource I2C_SCR: Bank 0 reg[D7] Status Control Register

Bus Error: Indicates a Bus Error condition is detected.

Lost Arbitration: In MultiMaster mode indicates loss of arbitration for this device (the device does not

control the bus).

Stop Status: An I

C stop condition has been detected.

ACK out: direct the I

C block to Acknowledge (1) or Not Acknowledge (0) a received byte.

Address: Received or transmitted byte is an address.

Last Received Bit (LRB): Value of last received bit (bit 9) in a transmit sequence, status of Ack/Nak from

destination device.

Byte Complete: 8 data bits have been received. For Receive Mode, the bus is stalled waiting for an

Ack/Nak. For Transmit Mode Ack Nak has also been received (see LRB) and the bus is stalled for the next

action to be taken.

Table 3. Resource I2C_DR: Bank 0 reg[D8] Data Register

Bit 7 6 5 4 3 2 1 0

Value Reserved PinSelect Bus Error

Stop IE Clock

Rate[1]

Clock

Rate[0]

Enable

Master

Enable

Slave

Bit 7 6 5 4 3 2 1 0

Value Bus Error Lost Arb Stop Status ACK out Address Transmit Last Rec’d

Bit (LRB)

Byte

Complete

Bit 7 6 5 4 3 2 1 0

Value Data

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 38 39

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