Cypress Semiconductor FX2LP Manuel d'utilisateur

EZ-USB FX2LP™ USB MicrocontrollerCY7C68013A/CY7C68014ACY7C68015A/CY7C68016ACypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 10 of 60EP2–1024 double buffered; EP6–512 quad buffered(column 8).3.12.5

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 11 of 603.13 External FIFO Interface3.13.1 ArchitectureThe FX2LP slave FI

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 12 of 603.15 ECC Generation[7]The EZ-USB can calculate ECCs (Error-Correc

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 13 of 603.20 CY7C68013A/14A and CY7C68015A/16A DifferencesCY7C68013A is i

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 14 of 604.0 Pin AssignmentsFigure 4-1 identifies all signals for the fiv

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 15 of 60RDY0RDY1CTL0CTL1CTL2INT0#/PA0INT1#/PA1PA2WU2/PA3PA4PA5PA6PA756BKP

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 16 of 60CLKOUTVCCGNDRDY0/*SLRDRDY1/*SLWRRDY2RDY3RDY4RDY5AVCCXTALOUTXTALIN

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 17 of 60PD0/FD8*WAKEUPVCCRESET#CTL5GNDPA7/*FLAGD/SLCS#PA6/*PKTENDPA5/FIFO

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 18 of 6012345678910111213141516171819202122232425262728PD5/FD13PD6/FD14PD

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 19 of 6028272625242322212019181716154344454647484950515253545556123456789

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 2 of 601.1 Features (CY7C68013A/14A only)• CY7C68014A: Ideal for battery

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 20 of 60Figure 4-6. CY7C68013A 56-pin VFBGA Pin Assignment - Top view1234

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 21 of 604.1 CY7C68013A/15A Pin Descriptions Table 4-1. FX2LP Pin Descrip

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 22 of 6034 28 BKPT Output L Breakpoint. This pin goes active (HIGH) when

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 23 of 6084 69 42 35 8F PA2 orSLOE orI/O/Z I(PA2)Multiplexed pin whose fun

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 24 of 6054 44 29 22 5H PB4 orFD[4]I/O/Z I(PB4)Multiplexed pin whose funct

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 25 of 60103 81 53 46 7A PD1 orFD[9]I/O/Z I(PD1)Multiplexed pin whose func

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 26 of 60112 90 PE4 orRXD1OUTI/O/Z I(PE4)Multiplexed pin whose function is

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 27 of 6070 55 37 30 7G CTL1 orFLAGBO/Z H Multiplexed pin whose function i

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 28 of 6051 41 RXD0 Input N/A RXD0 is the active-HIGH RXD0 input to 8051 U

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 29 of 605.0 Register SummaryFX2LP register bit definitions are described

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 3 of 603.0 Functional Overview3.1 USB Signaling SpeedFX2LP operates at t

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 30 of 60E62E 1 ECC2B1 ECC2 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 L

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 31 of 60E662 1 USBERRIE USB Error Interrupt EnablesISOEP8 ISOEP6 ISOEP4 I

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 32 of 60E6A4 1 EP4CS Endpoint 4 Control and Status0 0 NPAK1 NPAK0 FULL EM

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 33 of 60reservedreservedE6D2 1 EP2GPIFFLGSEL[11]Endpoint 2 GPIF Flag sele

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 34 of 6088 1 TCON Timer/Counter Control(bit addressable)TF1 TR1 TF0 TR0 I

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 35 of 60D0 1 PSW Program Status Word (bit addressable)CY AC F0 RS1 RS0 OV

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 36 of 606.0 Absolute Maximum RatingsStorage Temperature ...

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 37 of 609.0 DC Characteristics Notes:16. Measured at Max VCC, 25°C.9.1 U

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 38 of 6010.2 Program Memory Read Notes:17. CLKOUT is shown with positive

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 39 of 6010.3 Data Memory Read data intCLA[15..0]tAVtAVRD#tSTBLtSTBHtDHD[7

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 4 of 603.5 USB Boot MethodsDuring the power-up sequence, internal logic c

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 40 of 6010.4 Data Memory Write When using the AUTPOPTR1 or AUTOPTR2 to ad

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 41 of 6010.5 PORTC Strobe Feature TimingsThe RD# and WR# are present in t

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 42 of 6010.6 GPIF Synchronous SignalsDATA(output)tXGDIFCLKRDYXDATA(input)

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 43 of 6010.7 Slave FIFO Synchronous ReadIFCLKSLRDFLAGSSLOEtSRDtRDHtOEontX

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 44 of 6010.8 Slave FIFO Asynchronous ReadSLRDFLAGStRDpwltRDpwhSLOEtXFLGtX

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 45 of 6010.9 Slave FIFO Synchronous WriteZZtSFDtFDHDATAIFCLKSLWRFLAGStWRH

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 46 of 6010.10 Slave FIFO Asynchronous Write10.11 Slave FIFO Synchronous P

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 47 of 60auto mode and it is desired to send two packets back to back:a fu

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 48 of 6010.13 Slave FIFO Output Enable 10.14 Slave FIFO Address to Flags/

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 49 of 6010.15 Slave FIFO Synchronous Address 10.16 Slave FIFO Asynchrono

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 5 of 60The FX2LP jump instruction is encoded as follows.If Autovectoring

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 50 of 6010.17 Sequence Diagram10.17.1 Single and Burst Synchronous Read E

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 51 of 6010.17.2 Single and Burst Synchronous Write The Figure 10-20 shows

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 52 of 6010.17.3 Sequence Diagram of a Single and Burst Asynchronous Read

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 53 of 6010.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 54 of 6011.0 Ordering InformationTable 11-1. Ordering InformationOrderi

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 55 of 6012.0 Package DiagramsThe FX2LP is available in five packages:• 5

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 56 of 60 Package Diagrams (continued)NOTE:1. JEDEC STD REF MS-0262. BODY

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 57 of 60Package Diagrams (continued)NOTE:1. JEDEC STD REF MS-0262. BODY L

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 58 of 6013.0 PCB Layout Recommendations[24]The following recommendations

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 59 of 60© Cypress Semiconductor Corporation, 2006. The information contai

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 6 of 60If Autovectoring is enabled (AV4EN = 1 in the INTSET-UPregister),

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 60 of 60Document History Page Document Title: CY7C68013A EZ-USB FX2LP™ U

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 7 of 60 3.9.2 Wakeup PinsThe 8051 puts itself and the rest of the chip i

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 8 of 60Figure 3-3. Internal Code Memory, EA = 0Inside FX2LP Outside FX2LP

CY7C68013A/CY7C68014ACY7C68015A/CY7C68016ADocument #: 38-08032 Rev. *K Page 9 of 603.11 Register Addresses3.12 Endpoint RAM3.12.1 Size• 3× 64 bytes (