Cypress Semiconductor CY7C1516KV18 Fiche technique télécharger pdf

72-Mbit DDR II SRAM 2-Word

Burst Architecture

CY7C1516KV18, CY7C1527KV18

CY7C1518KV18, CY7C1520KV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-00437 Rev. *J Revised April 10, 2011

Features

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 333 MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces

(data transferred at 666 MHz) at 333 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Synchronous internally self-timed writes

■ DDR II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to DDR I device with 1 cycle read latency when

DOFF

is asserted LOW

■ 1.8 V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4 V–V

)

❐ Supports both 1.5 V and 1.8 V IO supply

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible Test Access Port

■ Phase-locked loop (PLL) for accurate data placement

Configurations

CY7C1516KV18 – 8M x 8

CY7C1527KV18 – 8M x 9

CY7C1518KV18 – 4M x 18

CY7C1520KV18 – 2M x 36

Functional Description

The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and

CY7C1520KV18 are 1.8 V synchronous pipelined SRAM

equipped with DDR II architecture. The DDR II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K

. Read data is

driven on the rising edges of C and C

if provided, or on the rising

edge of K and K

if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1516KV18

and two 9-bit words in the case of CY7C1527KV18 that burst

sequentially into or out of the device. The burst counter always

starts with a “0” internally in the case of CY7C1516KV18 and

CY7C1527KV18. On CY7C1518KV18 and CY7C1520KV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1518KV18 and two 36-bit words in the case of

CY7C1520KV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 333 300 250 200 167 MHz

Maximum Operating Current x8 510 480 420 370 340 mA

x9 510 480 420 370 340

x18 520 490 430 380 340

x36 640 600 530 450 400

[+] Feedback

1 2 3 4 5 6 ... 32 33

Résumé du contenu

Page 1 - Burst Architecture

72-Mbit DDR II SRAM 2-WordBurst ArchitectureCY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Cypress Semiconductor Corporation • 198 Champion Court

Page 2

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 10 of 33Programmable ImpedanceAn external resistor, RQ, mu

Page 3

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 11 of 33Truth TableThe truth table for the CY7C1516KV18, C

Page 4

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 12 of 33Write Cycle DescriptionsThe write cycle descriptio

Page 5

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 13 of 33IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs

Page 6

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 14 of 33IDCODEThe IDCODE instruction loads a vendor-specif

Page 7

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 15 of 33TAP Controller State DiagramThe state diagram for

Page 8

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 16 of 33TAP Controller Block DiagramTAP Electrical Charact

Page 9

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 17 of 33TAP AC Switching Characteristics Over the Operatin

Page 10 - CY7C1518KV18, CY7C1520KV18

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 18 of 33Identification Register Definitions Instruction Fi

Page 11

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 19 of 33Boundary Scan Order Bit # Bump ID Bit # Bump ID Bi

Page 12

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 2 of 33Logic Block Diagram (CY7C1516KV18)Logic Block Diagr

Page 13

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 20 of 33Power Up Sequence in DDR II SRAMDDR II SRAMs must

Page 14

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 21 of 33Maximum RatingsExceeding maximum ratings may impai

Page 15

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 22 of 33IDD[19]VDD operating supply VDD = Max,IOUT = 0 mA,

Page 16

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 23 of 33ISB1Automatic power down currentMax VDD, Both Port

Page 17 - [+] Feedback

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 24 of 33CapacitanceTested initially and after any design o

Page 18

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 25 of 33Switching Characteristics Over the Operating Range

Page 19

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 26 of 33Output TimestCOtCHQVC/C clock rise (or K/K in sing

Page 20 - PLL Constraints

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 27 of 33Switching WaveformsFigure 5. Read/Write/Deselect

Page 21

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 28 of 33Ordering Information The following table contains

Page 22

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 29 of 33Ordering Code DefinitionTemperature Range: X = C o

Page 23

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 3 of 33Logic Block Diagram (CY7C1518KV18)Logic Block Diagr

Page 24 - Thermal Resistance

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 30 of 33Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x

Page 25

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 31 of 33Acronyms Document ConventionsUnits of MeasureAcron

Page 26

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 32 of 33Document History PageDocument Title: CY7C1516KV18/

Page 27

Document Number: 001-00437 Rev. *J Revised April 10, 2011 Page 33 of 33QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Page 28

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 4 of 33ContentsPin Configuration ...

Page 29

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 5 of 33Pin Configuration The pin configurations for CY7C15

Page 30 - Package Diagram

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 6 of 33CY7C1518KV18 (4M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ A

Page 31

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 7 of 33Pin Definitions Pin Name I/O Pin DescriptionDQ[x:0]

Page 32

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 8 of 33CQ Output Clock CQ referenced with respect to C. Th

Page 33

CY7C1516KV18, CY7C1527KV18CY7C1518KV18, CY7C1520KV18Document Number: 001-00437 Rev. *J Page 9 of 33Functional OverviewThe CY7C1516KV18, CY7C1527KV18,

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