Cypress Semiconductor CYV15G0404DXB Guide de l'utilisateur télécharger pdf (Page 4)

CYV15G0404DXB Evaluation Board

Users Guide

Page 4 of 56

LIST OF TABLES

Table 5-1. Description of Connectors of the CYV15G0404DXB Evaluation Board ............................. 11

Table 5-2. Description of External Control Pins for Connectors J31 to J41 ......................................... 14

Table 5-3. Device Control Latch Description ....................................................................................... 14

Table 5-4. Device Control Latch Configuration .................................................................................... 16

Table 6-1. Device Control Latch Configuration Example ..................................................................... 18

Table 7-1. Device Control Latch Configuration for BIST on Channel A ............................................... 21

Table 7-2. Device Control Latch Configuration Table for Global Configuration ................................... 23

Table 7-3. Device Control Latch Configuration for Parallel Data Test Mode ....................................... 25

Table 7-4. Input Register Bit Assignments .......................................................................................... 26

Table 7-5. Output Register Bit Assignments ........................................................................................ 26

Table 7-6. Device Control Latch Configuration for Parallel Data Test Mode, Unencoded ................... 27

Table 7-7. Device Control Latch Configuration for Bist on Channel A ................................................. 29

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Cypress Semiconductor CYV15G0404DXB Guide de l'utilisateur Page 4