Cypress Semiconductor Perform CY8C21x23 Manuel d'utilisateur télécharger pdf (Page 27)

February 25, 2005 Document No. 38-12022 Rev. *G 27

CY8C21x23 Final Data Sheet 3. Electrical Specifications

3.4.6 AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T

≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C

and are for design guidance only.

3.4.7 AC I

C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 3-24. AC Programming Specifications

Symbol Description Min Typ Max Units Notes

RSCLK

Rise Time of SCLK 1 – 20 ns

FSCLK

Fall Time of SCLK 1 – 20 ns

SSCLK

Data Set up Time to Falling Edge of SCLK 40 – – ns

HSCLK

Data Hold Time from Falling Edge of SCLK 40 – – ns

SCLK

Frequency of SCLK 0 – 8 MHz

ERASEB

Flash Erase Time (Block) – 15 – ms

WRITE

Flash Block Write Time – 30 – ms

DSCLK3

Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

DSCLK2

Data Out Delay from Falling Edge of SCLK – – 70 ns 2.4 ≤ Vdd ≤ 3.0

Table 3-25. AC Characteristics of the I

C SDA and SCL Pins for Vcc ≥ 3.0V

Symbol Description

Standard Mode Fast Mode

Units NotesMin Max Min Max

SCLI2C

SCL Clock Frequency 0 100 0 400 kHz

HDSTAI2C

Hold Time (repeated) START Condition. After this period,

the first clock pulse is generated.

4.0 –0.6– µs

LOWI2C

LOW Period of the SCL Clock 4.7 –1.3– µs

HIGHI2C

HIGH Period of the SCL Clock 4.0 –0.6– µs

SUSTAI2C

Set-up Time for a Repeated START Condition 4.7 –0.6– µs

HDDATI2C

Data Hold Time 0 –0– µs

SUDATI2C

Data Set-up Time

250

–

100

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

SU;DAT

≥ 250 ns must then be met. This will automatically be the case if

the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

rmax

+ t

SU;DAT

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

–

SUSTOI2C

Set-up Time for STOP Condition 4.0 –0.6– µs

BUFI2C

Bus Free Time Between a STOP and START Condition 4.7 –1.3– µs

SPI2C

Pulse Width of spikes are suppressed by the input filter. – – 0 50 ns

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