Cypress Semiconductor Perform CY8C21x23 Manuel d'utilisateur télécharger pdf (Page 28)

February 25, 2005 Document No. 38-12022 Rev. *G 28

CY8C21x23 Final Data Sheet 3. Electrical Specifications

Figure 3-6. Definition for Timing for Fast/Standard Mode on the I

C Bus

Table 3-26. 2.7V AC Characteristics of the I

C SDA and SCL Pins (Fast Mode not Supported)

Symbol Description

Standard Mode Fast Mode

Units NotesMin Max Min Max

SCLI2C

SCL Clock Frequency 0 100 ––kHz

HDSTAI2C

Hold Time (repeated) START Condition. After this period,

the first clock pulse is generated.

4.0 – – – µs

LOWI2C

LOW Period of the SCL Clock 4.7 – – – µs

HIGHI2C

HIGH Period of the SCL Clock 4.0 – – – µs

SUSTAI2C

Set-up Time for a Repeated START Condition 4.7 – – – µs

HDDATI2C

Data Hold Time 0 – – – µs

SUDATI2C

Data Set-up Time 250 – – –ns

SUSTOI2C

Set-up Time for STOP Condition 4.0 – – – µs

BUFI2C

Bus Free Time Between a STOP and START Condition 4.7 ––– µs

SPI2C

Pulse Width of spikes are suppressed by the input filter. – –––ns

SCL

BUFI2C

SPI2C

HDSTAI2C

LOWI2C

SUDATI2C

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Cypress Semiconductor Perform CY8C21x23 Manuel d'utilisateur Page 28