Cypress Semiconductor Perform CY8C21x23 Manuel d'utilisateur télécharger pdf (Page 29)

February 25, 2005 Document No. 38-12022 Rev. *G 29

4. Packaging Information

This chapter illustrates the packaging specifications for the CY8C21x23 PSoC device, along with the thermal impedances for each

package and minimum solder reflow peak temperature.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/support/link.cfm?mr=poddim.

4.1 Packaging Dimensions

Figure 4-1. 8-Lead (150-Mil) SOIC

SEATING PLANE

PIN1ID

0.230[5.842]

0.244[6.197]

0.157[3.987]

0.150[3.810]

0.189[4.800]

0.196[4.978]

0.050[1.270]

BSC

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.0098[0.249]

0.0138[0.350]

0.0192[0.487]

0.016[0.406]

0.035[0.889]

0.0075[0.190]

0.0098[0.249]

1. DIMENSIONS IN INCHES[MM] MIN.

MAX.

0°~8°

0.016[0.406]

0.010[0.254]

X 45°

2. PIN 1 ID IS OPTIONAL,

ROUND ON SINGLE LEADFRAME

RECTANGULAR ON MATRIX LEADFRAME

0.004[0.102]

3. REFERENCE JEDEC MS-012

PART #

S08.15 STANDARD PKG.

SZ08.15 LEAD FREE PKG.

4. PACKAGE WEIGHT 0.07gms

51-85066 *C

1 2 ... 24 25 26 27 28 29 30 31 32 33

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