Cypress Semiconductor FX2LP Manuel d'utilisateur télécharger pdf (Page 44)

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10.8 Slave FIFO Asynchronous Read

SLRD

FLAGS

RDpwl

RDpwh

SLOE

XFLG

XFD

DATA

OEon

OEoff

N+1

Figure 10-8. Slave FIFO Asynchronous Read Timing Diagram

[20]

Table 10-8. Slave FIFO Asynchronous Read Parameters

[23]

Parameter Description Min. Max. Unit

RDpwl

SLRD Pulse Width LOW 50 ns

RDpwh

SLRD Pulse Width HIGH 50 ns

XFLG

SLRD to FLAGS Output Propagation Delay 70 ns

XFD

SLRD to FIFO Data Output Propagation Delay 15 ns

OEon

SLOE Turn-on to FIFO Data Valid 10.5 ns

OEoff

SLOE Turn-off to FIFO Data Hold 10.5 ns

Note:

23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.

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Cypress Semiconductor FX2LP Manuel d'utilisateur Page 44