Cypress Semiconductor FX2LP Manuel d'utilisateur télécharger pdf (Page 50)

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10.17 Sequence Diagram

10.17.1 Single and Burst Synchronous Read Example

Figure 10-18 shows the timing relationship of the SLAVE FIFO

signals during a synchronous FIFO read using IFCLK as the

synchronizing clock. The diagram illustrates a single read

followed by a burst read.

• At t = 0 the FIFO address is stable and the signal SLCS is

asserted (SLCS may be tied low in some applications).

Note: t

SFA

has a minimum of 25 ns. This means when IFCLK

is running at 48 MHz, the FIFO address set-up time is more

than one IFCLK cycle.

• At t = 1, SLOE is asserted. SLOE is an output enable only,

whose sole function is to drive the data bus. The data that

is driven on the bus is the data that the internal FIFO pointer

is currently pointing to. In this example it is the first data

value in the FIFO. Note: the data is pre-fetched and is driven

on the bus when SLOE is asserted.

• At t = 2, SLRD is asserted. SLRD must meet the set-up time

of t

SRD

(time from asserting the SLRD signal to the rising

edge of the IFCLK) and maintain a minimum hold time of

RDH

(time from the IFCLK edge to the deassertion of the

SLRD signal). If the SLCS signal is used, it must be asserted

before SLRD is asserted (i.e., the SLCS and SLRD signals

must both be asserted to start a valid read condition).

• The FIFO pointer is updated on the rising edge of the IFCLK,

while SLRD is asserted. This starts the propagation of data

from the newly addressed location to the data bus. After a

propagation delay of t

XFD

(measured from the rising edge

of IFCLK) the new data value is present. N is the first data

value read from the FIFO. In order to have data on the FIFO

data bus, SLOE MUST also be asserted.

The same sequence of events are shown for a burst read and

are marked with the time indicators of T = 0 through 5. Note:

For the burst mode, the SLRD and SLOE are left asserted

during the entire duration of the read. In the burst read mode,

when SLOE is asserted, data indexed by the FIFO pointer is

on the data bus. During the first read cycle, on the rising edge

of the clock the FIFO pointer is updated and increments to

point to address N+1. For each subsequent rising edge of

IFCLK, while the SLRD is asserted, the FIFO pointer is incre-

mented and the next data value is placed on the data bus.

IFCLK

SLRD

FLAGS

SLOE

DATA

Figure 10-18. Slave FIFO Synchronous Read Sequence and Timing Diagram

[20]

SRD

RDH

OEon

XFD

XFLG

IFCLK

N+1

Data Driven: N

>= t

SRD

OEon

XFD

N+2

XFD

>= t

RDH

OEoff

N+4

N+3

OEoff

SFA

FAH

FIFOADR

SLCS

t=0

N+1

t=1

t=2

t=3

t=4

FAH

T=0

SFA

T=1

T=2

T=3

T=4

N+1 N+2

FIFO POINTER

N+3

FIFO DATA BUS

N+4

Not Driven Driven: N

SLOE

SLRD

N+1 N+2

N+3

Not Driven

SLRD

SLOE

IFCLK

Figure 10-19. Slave FIFO Synchronous Sequence of Events Diagram

IFCLK IFCLK

N+4

IFCLK IFCLK

SLRD

N+1

SLRD

N+1

SLOE

Not Driven

N+4

IFCLK

SLOE

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 59 60

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