Cypress Semiconductor enCoRe CY7C601xx Guide de l'utilisateur

enCoRe™ II Low VoltageMicrocontrollerCY7C601xxCY7C602xxCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-260

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 10 of 62ExamplesSource DirectThe result of an instruction using this addressing mode isplaced in eit

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 11 of 62Destination Direct Source ImmediateThe result of an instruction using this addressing mode i

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 12 of 62Instruction Set SummaryThe instruction set is summarized in Ta ble 1 9 numerically and serve

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 13 of 621A 6 2 SBB A, [expr] C, Z 47 8 3 TST [expr], expr Z 74 4 1 INC A C, Z1B 7 2 SBB A, [X+ex

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 14 of 62Memory OrganizationFlash Program Memory OrganizationFigure 3. Program Memory Space with Inte

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 15 of 62Data Memory OrganizationThe CY7C601xx/CY7C602xx microcontrollers provide up to 256 bytes of

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 16 of 62Two important variables that are used for all functions areKEY1 and KEY2. These variables ar

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 17 of 62The configuration of the WriteBlock function is straightforward.The BLOCKID of the Flash blo

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 18 of 62EraseAll FunctionThe EraseAll function performs a series of steps that destroythe user data

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 19 of 62ClockingThe enCoRe II LV internal oscillator outputs two frequencies,the Internal 24 MHz Osc

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 2 of 62The enCoRe II LV features an internal oscillator. Optionally, anexternal 1 MHz to 24 MHz crys

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 20 of 62On the CY7C601xx, the external oscillator can be sourced bythe crystal oscillator or when th

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 21 of 62Table 32.CPU Clock Config (CPUCLKCR) [0x30] [R/W] Bit # 7 6 5 4 3 2 1 0Field Reserved CPUCLK

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 22 of 62Interval Timer Clock (ITMRCLK)The Interval Timer clock (ITMRCLK), can be sourced from theext

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 23 of 62Figure 6. Programmable Interval Timer Block DiagramTimer Capture Clock (TCAPCLK)The Timer Ca

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 24 of 62Table 35.Timer Clock Config (TMRCLKCR) [0x31] [R/W]Bit # 7 6 5 4 3 2 1 0Field TCAPCLK Divide

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 25 of 62Internal Clock TrimExternal Clock TrimTable 36.IOSC Trim (IOSCTR) [0x34] [R/W] Bit # 7 6 5 4

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 26 of 62LPOSC TrimCPU Clock During Sleep ModeWhen the CPU enters sleep mode the CPUCLK Select (Bit 0

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 27 of 62Power-On ResetPOR occurs every time the power to the device is switched on.POR is released w

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 28 of 62Sleep ModeThe CPU can only be put to sleep by the firmware. This isaccomplished by setting t

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 29 of 62Figure 8. Sleep TimingWakeup SequenceOnce asleep, the only event that can wake the system up

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 3 of 62Packages/PinoutsFigure 2. Package Configurations1234569111516171819202221NCP0.7TIO1/P0.6TIO0/

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 30 of 62Figure 9. Wakeup TimingINTSLEEPPDBANDGAPCLK32KSAMPLESAMPLE LVD/PORCPUCLK/24MHzBRABRQENABLECP

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 31 of 62Low-Voltage Detect Control POR Compare StateTable 41.Low-voltage Control Register (LVDCR) [0

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 32 of 62ECO Trim RegisterGeneral Purpose I/O PortsPort Data RegistersP0 Data Table 43.ECO (ECO_TR) [

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 33 of 62P1 DataP2 Data P3 Data P4 Data Table 45.P1 Data Register (P1DATA) [0x01] [R/W]Bit # 7 6 5 4

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 34 of 62GPIO Port ConfigurationAll the GPIO configuration registers have common configu-ration contr

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 35 of 62P0.0/CLKIN ConfigurationP0.1/CLKOUT ConfigurationTable 49.P0.0/CLKIN Configuration (P00CR) [

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 36 of 62P0.2/INT0–P0.4/INT2 ConfigurationP0.5/TIO0–P0.6/TIO1 ConfigurationP0.7 Configuration Table 5

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 37 of 62P1.0 ConfigurationP1.1 ConfigurationP1.2 ConfigurationTable 54.P1.0 Configuration (P10CR) [0

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 38 of 62P1.3 Configuration (SSEL) P1.4–P1.6 Configuration (SCLK, SMOSI, SMISO) P1.7 Configuration Ta

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 39 of 62P2 Configuration P3 Configuration P4 Configuration Table 60.P2 Configuration (P2CR) [0x15] [

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 4 of 62Pin AssignmentsTable 1. Pin Assignments48 SSOP40 PDIP28 SSOP24QSOP24SOIC24PDIPName Descriptio

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 40 of 62Serial Peripheral Interface (SPI)The SPI Master/Slave Interface core logic runs on the SPI c

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 41 of 62SPI Data RegisterWhen an interrupt occurs to indicate to firmware that an byte of receive da

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 42 of 62 Table 65.SPI Mode Timing vs. LSB First, CPOL and CPHALSB First CPHA CPOL Diagram00000101001

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 43 of 62SPI Interface PinsThe SPI interface uses the P1.3–P1.6 pins. These pins areconfigured using

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 44 of 62Time CaptureenCoRe II LV has two 8-bit captures. Each capture hasseparate register for the r

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 45 of 62Table 70.Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W]Bit # 7 6 5 4 3 2 1 0Field Reserved

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 46 of 62‘Programmable Interval TimerTable 74.Timer Capture 1 Falling (TCAP1F) [0x25] [R/W]Bit # 7 6

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 47 of 62Figure 14. Timer Functional Timing DiagramTable 78.Programmable Interval Reload Low (PIRL) [

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 48 of 62Figure 15. 16-bit Free Running Counter Loading Timing DiagramFigure 16. Memory Mapped Regist

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 49 of 62Interrupt ControllerThe interrupt controller and its associated registers allow theuser’s co

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 5 of 6222 18 12 8 8 15 P0.1/CLKOUT GPIO Port 0 bit 1—Configured individuallyOn CY7C601xx, optional c

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 50 of 62Interrupt ProcessingThe sequence of events that occur during interrupt processingis as follo

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 51 of 62Interrupt Mask RegistersThe Interrupt Mask Registers (INT_MSKx) are used to enablethe indivi

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 52 of 62Table 85.Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]Bit # 7 6 5 4 3 2 1 0Field Reserved GPIO Po

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 53 of 62Interrupt Vector Clear RegisterTable 87. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W]Bit # 7 6 5

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 54 of 62Absolute Maximum RatingsStorage Temperature ...–65°C to +150°

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 55 of 62Figure 18. Clock TimingFigure 19. GPIO Timing DiagramSPI TimingTSMCKSPI Master Clock Rate FC

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 56 of 62Figure 20. SPI Master Timing, CPHA = 1Figure 21. SPI Slave Timing, CPHA = 1MSBTMSULSBTMHDTSC

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 57 of 62Figure 22. SPI Master Timing, CPHA = 0 Figure 23. SPI Slave Timing, CPHA = 0 MSBTMSULSBTMHDT

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 58 of 62 1 Ordering InformationOrdering Code FLASH Size RAM Size Package TypeCY7C60123-PVXC 8K 256 4

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 59 of 62Figure 25. 24-Lead (300-Mil) PDIP P13Figure 26. 24-lead QSOP O241Package Diagrams (continued

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 6 of 62Register SummaryenCoRe II LV Register SummaryAddr Name 7 6 5 4 3 2 1 0 R/W Default00 P0DATA P

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 60 of 62Figure 27. 28-Lead (5.3 mm) Shrunk Small Outline Package O28Figure 28. 40-Lead (600-Mil) Mol

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 61 of 62© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 62 of 62Document History PageDocument Title: CY7C601/2xx enCoRe™ II Low Voltage MicrocontrollerDocum

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 7 of 62Note: In the R/W column, b = Both Read and Writer = Read Onlyw = Write Onlyc = Read/Cleard =

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 8 of 62The Stack Pointer Register (CPU_SP) holds the address of thecurrent top-of-stack in the data

CY7C601xxCY7C602xxDocument 38-16016 Rev. *C Page 9 of 62Index Register Stack Pointer RegisterCPU Program Counter High RegisterCPU Program Counter Low