CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C Page 19 of 62
Clocking
The enCoRe II LV internal oscillator outputs two frequencies,
the Internal 24 MHz Oscillator and the 32 kHz Low-power
Oscillator.
The Internal 24 MHz Oscillator is designed such that it may be
trimmed to an output frequency of 24 MHz over temperature
and voltage variation. The Internal 24 MHz Oscillator accuracy
is 24 MHz –22% to +10% (between 0° and 70°C). No external
components are required to achieve this level of accuracy.
Firmware is responsible for selecting the correct trim values
from the User row to match the power supply voltage in the
end application and writing the values to the trim registers
IOSCTR and LPOSCTR.
The internal low-speed oscillator of nominally 32 kHz provides
a slow clock source for the enCoRe II LV in suspend mode,
particularly to generate a periodic wake-up interrupt and also
to provide a clock to sequential logic during power-up and
power-down events when the main clock is stopped. In
addition, this oscillator can also be used as a clocking source
for the Interval Timer clock (ITMRCLK) and Capture Timer
clock (TCAPCLK). The 32 kHz Low-power Oscillator can
operate in low-power mode or can provide a more accurate
clock in normal mode. The Internal 32 kHz Low-power Oscil-
lator accuracy ranges from –53.12% to +56.25%. The 32 kHz
low power oscillator can be calibrated against the internal 24
MHz oscillator or another timing source if desired.
enCoRe II LV provides the ability to load new trim values for
the 24-MHz oscillator based on voltage. This allows Vdd to be
monitored and have firmware trim the oscillator based on
voltage present. The IOSCTR register is used to set trim
values for the 24-MHz oscillator. enCoRe II LV is initialized with
3.30V trim values at power-on, then firmware is responsible for
transferring the correct set of trim values to the trim registers
to match the application’s actual Vdd. The 32 kHz oscillator
generally does not require trim adjustments vs. voltage but
trim values for the 32 kHz are also stored in Supervisory ROM.
When using the 32 kHz oscillator the PITMRL/H should be
read until 2 consecutive readings match before
sending/receiving data. The following firmware example
assumes the developer is interested in the lower byte of the
PIT.
Read_PIT_counter:
mov A, reg[PITMRL]
mov [57h], A
mov A, reg[PITMRL]
mov [58h],A
mov [59h], A
mov A, reg[PITMRL]
mov [60h], A
;;;Start comparison
mov A,[60h]
mov X, [59h]
sub A, [59h]
jz done
mov A, [59h]
mov X, [58h]
sub A, [58h]
jz done
mov X, [57h]
;;;correct data is in memory location 57h
done:
mov [57h], X
ret
The CY7C601xx part can optionally be sourced from an
external crystal oscillator. The external clock driving on CLKIN
range is from 187 KHz to 24 MHz.
Clock Architecture Description
The enCoRe II LV clock selection circuitry allows the selection
of independent clocks for the CPU, Interval Timers and
Capture Timers.
Table 30.Checksum Parameters
Name Address Description
KEY1 0,F8h 3Ah
KEY2 0,F9h Stack Pointer value when SSC is
executed
BLOCKID 0,FAh Number of Flash blocks to calculate
checksum on
Table 31.Oscillator Trim Values vs. Voltage Settings
Supervisory FLASH
User Row Address
Function
0xC094 24-MHz IOSCTR @ 3.30V
0xC095 24-MHz IOSCTR @ 3.00V
0xC096 24-MHz IOSCTR @ 2.85V
0xC097 24-MHz IOSCTR @ 2.70V
(28 pages)
(88 pages)
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