Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur télécharger pdf (Page 27)

File

extension

Contents What to Look For

.BLD The output from the NGDBuild

process that link all the logic

together

There should be no errors. This program issues

numerous warnings but there should be no

errors. Most link errors occur because of missing

netlist files – Coregen put the files somewhere

else, or a missing netlist from a black box.

.MAP The output from the MAP process

that does the logic mapping to the

physical device. Removes

unused logic and.

There should be no errors, but warnings are

usually OK. Common problems range from

incompatible logic mappings, impossible area

constraints, and clock connections.

.PAR The output of the Place and

Route implementation process.

Shows timing results and fit

results.

Timing constraints should be met. Review the

summary at the end of this report to see if timing

is OK since it will complete no matter how bad it

is. Also look for any incomplete routing.

.BGN The output of the Bitgen tool. Normally, this is not a problem. Occasionally

though the design will route but not complete

Bitgen will report this error.

Table 4: Xilinx Report Files Generated During Implemention

In many designs, you will have to resolve timing problems that are shown in the place and route

process. Xilinx has several tools to help find the problems; Timing Analyzer is usually the place to

start. This tool helps you to understand the reason the logic did not meet timing – too many

connections, bad routing, etc. The tool suggests how to fix it. This is usually helpful but may

mean you are back to functional simulation again to add pipelining or change the logic and must

re-implement the design.

Once you achieve one good result, you may want to switch to incremental mode in the tool. This

allows you to use the last good result for most of the design that is unchanged when minor fixes

are made. For big changes however, you will need to reroute the whole chip.

Expect that the implementation process will be in the range of ½ to 2 hours in length depending

on your computer, how easy it is to meet constraints and how big the chip is. A tightly packed,

fast big chip will take a while. A VP40 that is 85% full, running at 130 MHz takes about 1.5 hours

to route on a Pentium 4 with 1 GB of RAM.

The final output of the implementation process is a .BIT file that represents the logic image. This

file is used to create a ROM image or for direct JTAG downloading.

5.4 Loading Logic

There are usually two methods of loading logic into the target FPGA : JTAG and from a PROM

image. JTAG is normally used during the development process because it is quick and easy to to

use. The ROM image is normally used after logic development is complete and the application is

deployed.

5.4.1 JTAG

Logic images may be loaded using the JTAG interface to the FPGA using a Xilinx JTAG cable

such as Parallel Cable IV or others. This provides a convenient method of quickly loading the

logic during the development process but is not usually used in deployed applications.

Innovative Integration FrameWork Logic User Guide 27

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