
Port Direction Function
fifo_rd_d[15:0] In Data bus to the PCI write FIFO from DSP EMIF B.
fifo_rd_en_n Out PCI read FIFO write enable, active low.
fifo_rd_oe_n Out PCI read FIFO output enable, active low.
fifo_wr_pae_n In PCI read FIFO almost empty, active low.
fifo_rd_or_n In PCI read FIFO output ready, active low.
fifo_eren In PCI read FIFO read enable echo.
fifo_erclk In PCI read FIFO read clock.
pci_fifo_wr_int Out PCI write FIFO interrupt to PCI controller.
pci_fifo_rd_int Out PCI read FIFO interrupt to PCI controller.
Table 18: ii_quixote_emif_b Component Ports
Target Devices : any
Innovative Integration FrameWork Logic User Guide 90
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