Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur télécharger pdf (Page 5)

Illustration 40: ChipScope Core Declarations................................................................... 43

Illustration 41: ChipScope Core Instantiation....................................................................44

Illustration 42: Xilinx ChipScope in Use...........................................................................45

Illustration 43: Quixote Logic and Peripherals.................................................................. 47

Illustration 44: Quixote Logic Block Diagram.................................................................. 48

Illustration 45: Quixote Logic Clock Domains..................................................................53

Illustration 46: Quixote A/D Interface and Application Logic.......................................... 54

Illustration 47: Quixote DAC Interface Block Diagram.................................................... 55

Illustration 48: TI DSP Asynchronous Memory Timing (Courtesy of Texas Instruments)...

Illustration 49: TI DSP Synchronous Memory Read Interface (Courtesy of Texas

Instruments)....................................................................................................................... 57

Illustration 50: TI DSP Synchronous Memory Write Interface (Courtesy of Texas

Instruments)....................................................................................................................... 57

Illustration 51: Quixote 6M Logic Utilization................................................................... 64

Illustration 52: Quixote 2M Logic Utilization................................................................... 65

Illustration 53: Quixote Area Constraint Logic Utilization............................................... 65

Illustration 54: Quixote Place and Route Report............................................................... 67

Illustration 55: Quixote Simulation Waveforms................................................................69

Illustration 56: PMC UWB Application Logic Block Diagram.........................................71

Illustration 57: ii_quixote_adc Block Diagram..................................................................73

Illustration 58Illustration 1Quixote ADC External FIFO Level Settings.......................... 75

Illustration 59: ii_quixote_dac Block Diagram..................................................................76

Illustration 60Quixote DAC External FIFO Level Settings...............................................78

Illustration 61: ii_quixote_emif_a Block Diagram............................................................ 80

Illustration 62: ii_quixote_emif_b Block Diagram............................................................88

Illustration 63: ii_quixote_clocks Block Diagram.............................................................91

Illustration 64: ii_quixote_pmc_j4 Block Diagram........................................................... 93

Illustration 65: ii_event_log Block Diagram......................................................................96

Innovative Integration FrameWork Logic User Guide 5

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Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur Page 5