Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur télécharger pdf (Page 54)

The data flows from the A/D into the external FIFO under control of the triggering logic. The

hardware interface component receives the data from the external FIFO then error corrects the

data. The data can optionally flow through a digital down-conversion (DDC) component or directly

into a data stacker. The DDC must be configured in the logic with filter coefficients to operate; the

as shipped version is not operable but shows hook-up to the component. The stacker packs four

data samples, two from each A/D into a 64-bit word. Finally, the data is moved into a destination

FIFO that is in the DSP EMIF A component.

If you need to modify the A/D signal chain to add signal processing, the best place is usually after

the A/D hardware component. This allows you to use the FIFO in the A/D hardware component

as a clock domain transition element and also gives you the A/D data directly from a FIFO. Once

the data has been flowed through the signal processing logic, it can then be inserted back into the

data flow to the DSP.

The A/D hardware interface component simply takes a trigger input and captures data when true.

The uber_trigger component supports many of the common types of triggering and produces a

trigger signal indicating when data is to be captured. Most applications use one of the many

trigger modes or need something similar. Triggering modes include capture a number of points,

capture for a length of time, capture above/below a threshold. The trigger may be started by a

DSP access, external input or other conditions. If you have a simple triggering method, you may

just put your own in that is less complex.

6.1.4.5 DAC Interface

The Quixote DAC interface uses a hardware interface component for the physical interface to the

DAC and external FIFO, ii_quixote_dac.vhd, and a support component in the application logic for

triggering, error correction and data flow control, dac_interface.vhd.

Here is a block digram of the DAC interface.

Innovative Integration FrameWork Logic User Guide 54

Illustration 46: Quixote A/D Interface and Application Logic

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Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur Page 54