Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur télécharger pdf (Page 97)

Port Direction Function

clk In Clock input

ce In Clock enable; unused

ref_clk In Reference clock for time stamping

reset In Master reset. Clears all pending events and FIFO.

d[31:0] In Data bus input.

event_in[31:0] In Event inputs. Rising edge of event inputs causes the

event log to make an alert record.

event_marker[31:0] In The event marker is put in the event message as word

event_class Out Event class signifies what type of alert is generated. For

event inputs 15..0, this is 1; for event inputs 31..16 this

is 0.

timestamp_run In Enables the time stamp counter to run.

ad_error_channel[7:0] In

dac_error_channel[7:0] In

event_dout[31:0] Out The output data from the alert FIFO.

event_fifo_not_empty Out When true, the event_fifo is not empty. More alert

messages, or a partial alert message, are in the FIFO.

event_fifo_rd In When true, this reads the alert FIFO. This signal must

be synchronous to clk. Each clock period will advance

the FIFO one element.

event_fifo_rst In Resets the event FIFO.

user_event_wr In An alert message may be created by writing to the data

port and asserting user_event_wr.

event_log_busy Out When true, the event log is busy creating a message.

Table 22: ii_event_log Component Ports

Target Device : Any Xilinx device

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Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur Page 97