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6.1.6.2 Constraints

There are several important classes of constraints used by the Framework Logic : timing, pin

placement and IO standards. These constraints are shown in the .ucf (user constraint file) that is

used during the fitting process.

The constraint files are different for the Quixote II (2M gates Virtex2) and Quixote III (6M gates

Virtex2) devices since they are in different packages. The 2M part is in a FF896 package; the 6M

part is in a FF1152 package.

Quixote Variant Logic Density Device Used Constraint File

Quixote II (80069-2) 2M Xilinx XC2V2000-4FF896C quix_intf_ff896.ucf

Quixote III (80069-3) 6M Xilinx XC2V6000-4FF1152C quix_intf_ff1152.ucf

Table 10: Quixote Constraint Files

6.1.6.2.1 Timing Constraints

The timing constraints defined cover the clocks used in the design and the external device signal

timing. Clock period period constraints are used to cover most of the logic since they define the

clock rate for all flip-flops connected to that clock. These period constraints then cover most of the

logic paths used in a synchronous design.

Here are the clock period constraints used by the Framework Logic:

TIMESPEC "TS_aeclkout1" = PERIOD "aeclkout1" 9.6 ns HIGH 50 %; # was 9.6 ns DPM 8/7/03

TIMESPEC "TS_adc_clk" = PERIOD "adc_clk" 10 ns HIGH 50 %; # created this so multicycle spec will

work

NET "beclkout1" PERIOD = 9.6 ns HIGH 50 %;

NET "adc0_clk" PERIOD = 10 ns ;

NET "adc0_clk_n" PERIOD = 10 ns ;

NET "adc0_wclk" PERIOD = 10 ns ;

NET "adc0_rclk" PERIOD = 10 ns ;

NET "adc1_clk" PERIOD = 10 ns ;

NET "adc1_clk_n" PERIOD = 10 ns ;

NET "adc1_wclk" PERIOD = 10 ns ;

NET "adc1_rclk" PERIOD = 10 ns ;

NET "dac0_wclk" PERIOD = 10 ns ;

NET "dac0_rclk" PERIOD = 10 ns ;

NET "dac1_wclk" PERIOD = 10 ns ;

NET "dac1_rclk" PERIOD = 10 ns ;

NET "adc_clk" PERIOD = 10 ns HIGH 50 %;

NET "dac_clk" PERIOD = 10 ns HIGH 50 %;

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Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur Page 61