Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur télécharger pdf (Page 69)

6.1.8.2 Simulation Models for Quixote

There are several models used in the Quixote simulations for system level testing.

Model Filename Functional Behavior

A/D 0 FIFO

Model

model_adc0fifo.vhd Provides a data ramp simulating the external A/D FIFO

output. For each read from the model on the rising edge

of the clock, one data point is provided. The ramp

increments from 0 to 65535 then repeats.

A/D 1 FIFO

Model

model_adc1fifo.vhd Provides a data ramp simulating the external A/D FIFO

output. For each read from the model on the rising edge

of the clock, one data point is provided. The ramp

decrements from 65535 to 0 then repeats.

SRAM Cy7c1372.vhd SRAM model provided by Cypress Semiconductor.

DAC FIFO model_dacfifo.vhd Provides a simple FIFO model for the level flags to help

debug data pacing.

PCI FIFO tb_fifo.vhd Provides a simple model for testing the PCI FIFO

interface.

Table 11: Quixote Simulation Models

Innovative Integration FrameWork Logic User Guide 69

Illustration 55: Quixote Simulation Waveforms

1 2 ... 64 65 66 67 68 69 70 71 72 73 74 ... 96 97

Pas de commentaire

Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur Page 69