Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur télécharger pdf (Page 60)

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downsample Illustrates the use of the A/D, DAC and SRAM components to make a

loop in the logic from A/D to DAC and includes simple decimation. The

downsample_hw logic is the hardware test version of this example.

emif_a_intf Shows how to use the DSP EMIF A component for status inputs, register

outputs, and FIFOs. The emif_a_intf_hw logic is the hardware test

version of this example.

loopback Shows use of A/D, DAC and SRAM component to loop the A/D to the

DAC. The loopback_hw logic is the hardware test version of this

example.

sram Illustrates use of the SRAM component. MATLAB can write in to the

RAM, then it plays back to a MATLAB scope. The sram_hw logic is the

hardware test version of this example.

sram_sinewave_fast_

access_test.

This example shows the use of the SRAM and DAC to make a high

speed arbitrary waveform generator. The SRAM is written directly from

MATLAB with a waveform, then played out at high-speed to the Quxiote

DAC. The sram_sinewave_fast_access_test_hw logic is the hardware

test version of this example.

adc_sinewave_sram This example shows how to make Quixote into a high speed

oscilloscope by capturing the A/D data in real-time to the SRAM. The

data can then be displayed from the SRAM into MATLAB. The

adc_sinewave_sram_hw logic is the hardware test version of this

example.

Table 8: MATLAB Examples for Quixote

6.1.6 Synthesis and Fitting

6.1.6.1 Getting Started

A project file for Quixote is provided for Xilinx ISE tool that provides all the project hierarchy,

included files and options required.

ISE Project File

quixote_intf_c.ise

Table 9: Quixote Xilinx ISE Project Filename

Since Quixote has two logic parts that are supported, two archives are provided. In each archive

the project file has the same name, but when the project is opened you will see that the logic part

is changed and also the constraints file.

If you are using Xilinx ISE, you should load this project as a starting point and recompile the logic

to verify that the project is ready to use. You should be able to successfully generate the BIT file

for the logic and run the examples on the card.

If you are using another synthesis tool, you will need to reconstruct the logic hierarchy as shown in

the HTML documentation in your toolset. The packages and libraries that support Xilinx parts

must be used since there are Xilinx-specific logic elements used in the design. These libraries

are provided by Xilinx for your simulation tool.

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