Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur télécharger pdf (Page 52)

6.1.4.3.1 Clock Sources

There are several clocks available to the designer in the logic that are intended for different

functions as shown in the following table.

The DSP EMIF clocks should be used for synchronizing to the DSP EMIF A or B buses. Since

these clocks are fixed frequency at ~100 MHz, a Digital Clock Manager (DCM) inside the Virtex2

should be used to reduce the clock skew in the chip, as is shown in the Framework Logic. These

clocks are not controlled for jitter or absolute frequency and should not be used for precision

timing operations or analog sample clocks.

The 20 MHz reference clock is a precision 20 MHz with about 5ppm of drift that may also be

accurately calibrated if necessary to use as a stable, accurate timebase. This clock is from a

temperature compensated crystal oscillator (TCXO) (Vectron P/N VTA2-1B0-20.0MHz) and is

very stable over time.

The PLL clock is normally used as the sample clock for the A/D and D/A. This is a software

programmable frequency source with very low jitter (<6 ps jitter) and resolutions of 200kHz. This

allows for multiple band sampling of IF in may RF applications. Since this clock must be low jitter

to preserve the analog signal quality, it is important in the logic design to preserve this quality of

clock. Do NOT use a DCM to manipulate this clock internally before sending to the analog

converters, since a DCM has large jitter of over 100 ps and your signal quality will be lost. If you

must divide the clock down, use a simple flip-flop divider for cleanest results. The PLL clock is

received as a differential PECL signal from the PLL directly into the Virtex2 logic and given to the

Spartan2 as LVTTL for use in the timing selection matrix.

The Quixote also supports clocks to be supplied from external sources such as PXI or as inputs

to the card. This supports multi-card synchronization and the use of custom external timebases.

These clocks are steered by the Spartan2 into the Virtex2 through a clock selection matrix. The

software library in Pismo supports clock steering and selection to two pins on the Virtex2 : ADCLK

and DACLK. These two clock sources may then be used in the Virtex2 for sampling and timing.

Clock Function Frequency Pin

6M Device

FF1152 Package

2M Device

FF896 Package

aeclkout1 DSP EMIF A clock ~100 MHz AE18 AD16

beclkout1 DSP EMIF B clock ~100 MHz AG17 AE15

refclk

(dds_src_clk)

Reference clock source 20.00 MHz, 5

ppm

AK17 AH15

ADC_CLK clock from Spartan2 clock

matrix

varies,

nominally 0-

100 MHz

E16 C14

DAC_CLK clock from Spartan2 clock

matrix

varies,

nominally 0-

100 MHz

H16 F14

PLL clock

(differentially

received)

Software programmable

sample

clock with <6 ps jitter

programmabl

e from

50-105 MHz

E19 (+)

E18 (-)

C17 (+)

C16 (-)

Table 7: Quixote Input Clocks

Innovative Integration FrameWork Logic User Guide 52

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 96 97

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