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Innovative Integration FrameWork Logic User Guide 64
Design Information
------------------
Command Line : C:/Xilinx/bin/nt/map.exe -ise
c:\projects\cquixote\logic\intf\rev2\amit\quixote_intf_c.ise -intstyle ise -p
xc2v6000-ff1152-4 -cm speed -ignore_keep_hierarchy -pr b -k 4 -c 100 -tx off -o
quixote_intf_map.ncd quixote_intf.ngd quixote_intf.pcf
Target Device : xc2v6000
Target Package : ff1152
Target Speed : -4
Mapper Version : virtex2 -- $Revision: 1.26.6.4 $
Mapped Date : Wed Sep 21 17:16:15 2005
Design Summary
--------------
Number of errors: 0
Number of warnings: 6
Logic Utilization:
Number of Slice Flip Flops: 8,687 out of 67,584 12%
Number of 4 input LUTs: 5,862 out of 67,584 8%
Logic Distribution:
Number of occupied Slices: 5,964 out of 33,792 17%
Number of Slices containing only related logic: 5,947 out of 5,964 99%
Number of Slices containing unrelated logic: 17 out of 5,964 1%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 7,501 out of 67,584 11%
Number used as logic: 5,862
Number used as a route-thru: 804
Number used as Shift registers: 835
Number of bonded IOBs: 552 out of 824 66%
IOB Flip Flops: 619
IOB Master Pads: 3
IOB Slave Pads: 3
Number of Block RAMs: 16 out of 144 11%
Number of MULT18X18s: 8 out of 144 5%
Number of GCLKs: 8 out of 16 50%
Number of DCMs: 2 out of 12 16%
Number of BSCANs: 1 out of 1 100%
Number of RPM macros: 21
Total equivalent gate count for design: 1,279,088
Additional JTAG gate count for IOBs: 26,496
Peak Memory Usage: 320 MB
Text 1: Quixote 6M Logic Utilization
Design Information
------------------
Command Line : C:/Xilinx/bin/nt/map.exe -ise
c:\projects\cquixote\logic\intf\rev2\amit\quixote_intf_c.ise -intstyle ise -p
xc2v6000-ff1152-4 -cm speed -ignore_keep_hierarchy -pr b -k 4 -c 100 -tx off -o
quixote_intf_map.ncd quixote_intf.ngd quixote_intf.pcf
Target Device : xc2v6000
Target Package : ff1152
Target Speed : -4
Mapper Version : virtex2 -- $Revision: 1.26.6.4 $
Mapped Date : Wed Sep 21 17:16:15 2005
Design Summary
--------------
Number of errors: 0
Number of warnings: 6
Logic Utilization:
Number of Slice Flip Flops: 8,687 out of 67,584 12%
Number of 4 input LUTs: 5,862 out of 67,584 8%
Logic Distribution:
Number of occupied Slices: 5,964 out of 33,792 17%
Number of Slices containing only related logic: 5,947 out of 5,964 99%
Number of Slices containing unrelated logic: 17 out of 5,964 1%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 7,501 out of 67,584 11%
Number used as logic: 5,862
Number used as a route-thru: 804
Number used as Shift registers: 835
Number of bonded IOBs: 552 out of 824 66%
IOB Flip Flops: 619
IOB Master Pads: 3
IOB Slave Pads: 3
Number of Block RAMs: 16 out of 144 11%
Number of MULT18X18s: 8 out of 144 5%
Number of GCLKs: 8 out of 16 50%
Number of DCMs: 2 out of 12 16%
Number of BSCANs: 1 out of 1 100%
Number of RPM macros: 21
Total equivalent gate count for design: 1,279,088
Additional JTAG gate count for IOBs: 26,496
Peak Memory Usage: 320 MB
Illustration 51: Quixote 6M Logic Utilization
- FrameWork Logic Users Guide 1
- 1 Table of Contents 2
- 2 List of Figures 4
- 3 List of Tables 6
- 4 Introduction 7
- 4.4 Where to Get Help 8
- 5 Logic Development Process 9
- Hardware Interface Layer 10
- Application 11
- (your logic does here) 11
- 5.1.2 VHDL Simulation 12
- 5.2.1 Installation 20
- 5.2.2 MATLAB Simulink Use 22
- SRAM used 24
- 5.4 Loading Logic 27
- 5.4.1 JTAG 27
- 5.4.2.2 Velocia Download 38
- 5.5 Debugging 39
- 5.5.1 Built-in Test Modes 39
- 5.5.2 Xilinx ChipScope 40
- CAUTION: 41
- 6 FrameWork Designs 46
- 6.1.4.2 Memory Map 48
- R/W CE Type 49
- 6.1.4.3 Clocks 51
- 6.1.4.3.1 Clock Sources 52
- 6.1.4.3.2 Domains 53
- 6.1.4.4 A/D Interface 53
- 6.1.4.5 DAC Interface 54
- 6.1.4.6 DSP Interface 55
- 6.1.4.6.1 DSP Bus EMIF A 55
- 6.1.4.6.2 DSP Bus EMIF B 59
- 6.1.4.7 Event Log 59
- 6.1.6 Synthesis and Fitting 60
- 6.1.6.2 Constraints 61
- 6.1.6.2.1 Timing Constraints 61
- 6.1.6.3 Logic Utilization 63
- 6.1.7 Place and Route 66
- 6.1.8 Simulation 68
- 6.1.8.3 Simulation notes 70
- 6.1.9.1 Loading over PCI 70
- 6.1.9.2 Loading over JTAG 70
- 6.2 PMC UWB 71
- 6.2.1 Overview 71
- 6.2.2 Target Devices 71
- 6.2.3 Development Tools 71
- 6.2.4 Application Example 71
- 7 Framework Library 72
- 7.1.1.1 ii_quixote_adc 73
- MATLAB Simulink Component: 75
- 7.1.1.2 ii_quixote_dac 76
- Supported Platforms: Quixote 79
- Description: 79
- Port Direction Function 81
- Target Devices: any 84
- MATLAB Simulink Components: 86
- Target Devices : any 90
- Target Device : Any 94
- 8 Generic Components 95
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