Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur télécharger pdf (Page 62)

NET "beclkout1" TNM_NET = "beclkout1";

NET "aeclkout1" TNM_NET = "aeclkout1";

As can be seen, EMIF A clock (aeclkout1) is contrained to 9.6 ns, giving a small margin for a 100

MHz bus. EMIF B (beclkout1) is similarly constrained to 9.6 ns. Other clocks include the highest

A./D and DAC clock rates.

External devices require an additional constraint to be sure that we get the signal on-chip and to

its destination in time. Since the external chip, such as the DSP, may have a delay from the clock

edge to when we get the signal, an additional constraint is defines the amount of time after the

clock that the signal is given to the logic. This type of constraint is used on the DSP control signals

such as CE, ARE, AWE and addresses to guarantee that setup timings are met. a Timing Group

is defined for these signals with a timing constraint for the group. There are more; this is an

example of this constraint type.

TIMESPEC "TS_DSP_FAST_CKIN" = FROM "DSP_FAST_CKIN" TO "FFS" 6 ns;

INST "ace_n<1>" TNM = "DSP_FAST_CKIN";

INST "ace_n<0>" TNM = "DSP_FAST_CKIN";

NET "aawe_n" TNM_NET = "DSP_FAST_CKIN";

NET "aare_n" TNM_NET = "DSP_FAST_CKIN";

NET "aaoe_n" TNM_NET = "DSP_FAST_CKIN";

INST "aea<22>" TNM = "DSP_FAST_CKIN";

INST "aea<21>" TNM = "DSP_FAST_CKIN";

INST "aea<20>" TNM = "DSP_FAST_CKIN";

INST "aea<19>" TNM = "DSP_FAST_CKIN";

INST "aea<18>" TNM = "DSP_FAST_CKIN";

INST "aea<17>" TNM = "DSP_FAST_CKIN";

INST "aea<16>" TNM = "DSP_FAST_CKIN";

Some of the registers used in the design do not require single clock cycles for readback, so a

multi-cycle clock specification is used. The following constraint is used for these types of registers

TIMESPEC "TS_dsp_regs" = FROM "DSP_FAST_CKIN" TO "dsp_emif_a_regs" "TS_aeclkout1" * 2;

and shows how these are specified as 2 clock cycles for analysis.

6.1.6.2.2 Physical Constraints

There are several types of physical constraints used in the design including location constraints

for pins, flip-flops forced into IOB cells, and area constraints for logic.

Pin location constraints should NEVER be changed since the PCB design requires this pin out.

It is also important to capture many of the high speed signals in the IOB registers for timing. This

is done using a constraint as in the constraint for the aaoe_n pin, an input from the DSP. Its IO

standard is LVTTL which is specified and the pin location is AJ24 for the FF896 package.

NET "aaoe_n" LOC = "AJ24" | IOSTANDARD = LVTTL ;

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Cypress Semiconductor Perform CY7C1372D Guide de l'utilisateur Page 62