
Chapter 4. Interrupts Page 4-13
SUTOK and SUDAV are supplied to the FX2 by CONTROL endpoint zero. The first portion of a
USB CONTROL transfer is the SETUP stage shown in Figure 4-3 (a full CONTROL transfer is
shown in Figure 2-1). When the FX2 decodes a SETUP packet, it asserts the SUTOK (SETUP
Token) Interrupt Request. After the FX2 has received the eight bytes error-free and copied them
into the eight internal registers at SETUPDAT, it asserts the SUDAV Interrupt Request.
Firmware responds to the SUDAV Interrupt by reading the eight SETUP data bytes in order to
decode the USB request (Chapter 2, "Endpoint Zero").
The SUTOK Interrupt is provided to give advance warning that the eight register bytes at
SETUPDAT are about to be overwritten. It is useful for debug and diagnostic purposes.
4.4.2.2 SOF Interrupt
Figure 4-4. A Start Of Frame (SOF) Packet
A USB Start-of-Frame Interrupt Request is asserted when the host sends a Start of Frame (SOF)
packet. SOFs occur once per millisecond in full-speed (12 Mbits/sec) mode, and once every 125
microseconds in high-speed (480 Mbits/sec) mode.
When the FX2 receives an SOF packet, it copies the eleven-bit frame number (FRNO in Figu re4-
4) into the USBFRAMEH:L registers and asserts the SOF Interrupt Request. All isochronous end-
point data is generally serviced via the SOF Interrupt.
4.4.2.3 Suspend Interrupt
If the FX2 detects a “suspend” condition from the host, it asserts the SUSP (Suspend) Interrupt
Request. A full description of Suspend-Resume signaling appears in Chapter 6, "Power Manage-
ment".
4.4.2.4 USB RESET Interrupt
The USB host signals a bus reset by driving both D+ and D- low for at least 10 ms. When the FX2
detects the onset of USB bus reset, it asserts the URES Interrupt Request.
4.4.2.5 HISPEED Interrupt
This interrupt is asserted when the host grants high-speed (480 Mbps) access to the FX2.
4.4.2.6 EP0ACK Interrupt
This interrupt is asserted when the FX2 has acknowledged the STATUS stage of a CONTROL
transfer on endpoint 0.
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