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Chapter 15. Registers Page 15-73

EP1OUTBUF is available for the firmware to read. USB OUT tokens for the endpoint are

NAK’d while BUSY=1 (the firmware is still reading data from the OUT endpoint).

A 1-to-0 transition of BUSY (indicating that the firmware can access the buffer) generates an

interrupt request for the OUT endpoint. After the firmware reads the data from the OUT end-

point buffer, it loads the endpoint’s byte count register with any value to re-arm the endpoint,

which automatically sets BUSY=1. This enables the OUT transfer of data from the host in

response to the next OUT token. The CPU should never read endpoint data while BUSY=1.

The BUSY bit, also indicates the status of the endpoint’s IN Buffer EP1INBUF. The USB core

sets BUSY=0 when the endpoint’s IN buffer is empty and ready for loading by the firmware.

The firmware sets BUSY=1 by loading the endpoint’s byte count register.

When BUSY=1, the firmware should not write data to an IN endpoint buffer, because the end-

point FIFO could be in the act of transferring data to the host over the USB. BUSY=0 when the

USB IN transfer is complete and endpoint RAM data is available for firmware access. USB IN

tokens for the endpoint are NAK’d while BUSY=0 (the firmware is still loading data into the

endpoint buffer).

A 1-to-0 transition of BUSY (indicating that the firmware can access the buffer) generates an

interrupt request for the IN endpoint. After the firmware writes the data to be transferred to the

IN endpoint buffer, it loads the endpoint’s byte count register with the number of bytes to trans-

fer, which automatically sets BUSY=1. This enables the IN transfer of data to the host in

response to the next IN token. Again, the CPU should never load endpoint data while

BUSY=1.

The firmware writes a “1” to an IN endpoint busy bit to disarm a previously armed endpoint.

(This sets BUSY=0.) The firmware should do this only after a USB bus reset, or when the host

selects a new interface or alternate setting that uses the endpoint. This prevents stale data

from a previous setting from being accepted by the host’s first IN transfer that uses the new

setting.

Bit 0 STALL OUT/IN Endpoint Stalled

Each bulk endpoint (IN or OUT) has a STALL bit in its Control and Status Register (bit 0). If the

CPU sets this bit, any requests to the endpoint return a STALL handshake rather than ACK or

NAK. The Get Status-Endpoint Request returns the STALL state for the endpoint indicated in

byte 4 of the request. Note that bit 7 of the endpoint number EP (byte 4) specifies direction.

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Cypress Semiconductor FX2LP Informations techniques Page 393