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Chapter 5. Memory Page 5-3

5.3 External Program Memory and External Data Memory

The standard 8051 employs a Harvard architecture for its External memory; the program and data

memories are physically separate. The FX2 uses a modified version of this memory model;

off-

chip

program and data memories are separate, but the

on-chip

program and data memories are

unified in a Von Neumann architecture. This allows the FX2’s on-chip RAM to be loaded from an

external source (USB or EEPROM, see

Chapter 3 "Enumeration and ReNumeration™"

), then

used as program memory.

Standard 8051

The standard 8051 has separate address spaces for program and data memory; it can address

64K of read-only program memory at addresses 0x0000-0xFFFF, and another 64K of read/write

data memory, also at addresses 0x0000-0xFFFF. The standard 8051 keeps the two memory

spaces separate by using different bus signals to access them; the read strobe for program mem-

ory is PSEN (Program Store Enable), and the read and write strobes for data memory are RD and

WR. The 8051 generates PSEN strobes for instruction fetches and for the MOVC (move code

memory into the accumulator) instruction; it generates RD and WR strobes for all data-memory

accesses. In a standard 8051 application, an external 64K ROM chip (enabled by the 8051’s

PSEN signal) might be used for program memory and an external 64K RAM chip (enabled by the

8051’s RD and WR signals) might be used for data memory.

In the standard 8051, all program memory is read-only.

FX2

The FX2 has 8K of on-chip RAM (the “Main RAM”) at addresses 0x0000-0x1FFF, and 512 bytes of

on-chip RAM (the “Scratch RAM”) at addresses 0xE000-0xE1FFF. Although this RAM is physically

located inside the chip, it’s addressed by FX2 firmware as External memory, just as though it were

in an external RAM chip.

Some systems use only this on-chip RAM, with no off-chip memory. In those systems, the RD and

PSEN strobes are automatically combined for accesses to addresses below 0x2000, so the Main

RAM is accessible as both data and program memory. The RD and PSEN strobes are not com-

bined for the Scratch RAM; Scratch RAM is accessible as data memory only.

Although it’s technically accurate to say that the Main RAM

data

memory is writable while the Main

RAM program memory is not, it’s a distinction without a difference. The Main RAM is accessible

both as program memory and data memory, so writing to Main RAM data memory is equivalent to

writing to Main RAM program memory at the same address.

The Scratch RAM is never accessible as program memory.

The FX2 also reserves 7.5K (0xE200-0xFFFF) of the data-memory address space for control/sta-

tus registers and endpoint buffers (see Section 5.6, "On-Chip Data Memory at 0xE000-0xFFFF").

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