Cypress Semiconductor FX2LP Informations techniques télécharger pdf (Page 13)

xiii

List of Figures

Figure 1-1. USB Packets ....................................................................................................................1-4

Figure 1-2. Two Bulk Transfers, IN and OUT .....................................................................................1-6

Figure 1-3. An Interrupt Transfer ........................................................................................................1-6

Figure 1-4. An Isochronous Transfer ..................................................................................................1-7

Figure 1-5. A Control Transfer ............................................................................................................1-7

Figure 1-6. What the SIE Does ...........................................................................................................1-9

Figure 1-7. FX2 56-pin Package Simplified Block Diagram ..............................................................1-11

Figure 1-8. FX2 128-pin Package Simplified Block Diagram ............................................................1-12

Figure 1-9. FX2 Block Diagram ........................................................................................................1-15

Figure 1-10. 56-pin, 100-pin, and 128-pin FX2 Packages ..................................................................1-16

Figure 1-11. Signals for the Three FX2 Package Types ....................................................................1-19

Figure 1-12. CY7C68013-128 TQFP Pin Assignment ........................................................................1-20

Figure 1-13. CY7C68013-100 TQFP Pin Assignment ........................................................................1-21

Figure 1-14. CY7C68013-56 SSOP Pin Assignment .........................................................................1-22

Figure 1-15. FX2 Endpoint Buffers .....................................................................................................1-23

Figure 1-16. FX2 FIFOs in “Slave FIFO” Mode ..................................................................................1-26

Figure 1-17. FX2 FIFOs in “GPIF Master” Mode ................................................................................1-27

Figure 2-1. A USB Control Transfer (With Data Stage) ......................................................................2-2

Figure 2-2. Two Interrupts Associated with EP0 CONTROL Transfers ..............................................2-3

Figure 2-3. Registers Associated with EP0 Control Transfers ...........................................................2-4

Figure 2-4. Data Flow for a Get_Status Request ...............................................................................2-7

Figure 2-5. Using Setup Data Pointer (SUDPTR) for Get_Descriptor Requests ..............................2-13

Figure 3-1. EEPROM Configuration Byte ...........................................................................................3-8

Figure 3-2. USB Control and Status Register ...................................................................................3-12

Figure 4-1. USB Interrupts ................................................................................................................4-10

Figure 4-2. The Order of Clearing Interrupt Requests is Important ..................................................4-12

Figure 4-3. SUTOK and SUDAV Interrupts ......................................................................................4-12

Figure 4-4. A Start Of Frame (SOF) Packet .....................................................................................4-13

Figure 4-5. The USB Autovector Mechanism in Action ....................................................................4-17

Figure 4-6. I²C-Compatible Bus Interrupt-Enable Bits and Registers ...............................................4-18

Figure 4-7. The FIFO/GPIF Autovector Mechanism in Action ..........................................................4-22

Figure 5-1. Internal Data RAM Organization ......................................................................................5-1

Figure 5-2. FX2 External Program/Data Memory Map, EA=0 ............................................................5-5

Figure 5-3. FX2 External Program/Data Memory Map, EA=1 ............................................................5-7

Figure 5-4. On-Chip Data Memory at 0xE000-0xFFFF ......................................................................5-9

Figure 6-1. Suspend-Resume Control ................................................................................................6-2

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 459 460

Pas de commentaire

Cypress Semiconductor FX2LP Informations techniques Page 13