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Chapter 15. Registers Page 15-29

15.6.3 Endpoint 2, 4, 6 and 8/Slave FIFO Configuration

Figure 15-24. Endpoint 2, 4, 6 and 8 /Slave FIFO Configuration

Bit 6 INFM1 IN Full Minus One

When a FIFO configuration register’s ‘INEARLY’ or INFM bit is set to 1, the FIFO flags for that

endpoint become valid one sample earlier than when the FULL condition occurs. These bits

take effect only when the FIFOS are operating synchronously—according to an internally- or

externally-supplied clock. Having the FIFO flag indications a clock early simplifies some syn-

chronous interfaces (applies only to IN endpoints).

Bit 5 OEP1 OUT Empty Plus One

When a FIFO configuration register’s ‘OUTEARLY’ or OEP1 bit is set to 1, the FIFO flags for

that endpoint become valid one sample earlier than when the EMPTY condition occurs. These

bits take effect only when the FIFOS are operating synchronously—according to an internally-

or externally-supplied clock. Having the FIFO flag indications a clock early simplifies some

synchronous interfaces (applies only to OUT endpoints).

Bit 4 AUTOOUT Instantaneous Connection to Endpoint FIFO

This bit applies only to OUT endpoints.

When AUTOOUT=1, as soon as a buffer fills with USB data, the buffer is automatically and

instantaneously committed to the endpoint FIFO bypassing the CPU. The endpoint FIFO flags

and buffer counts immediately indicate the change in FIFO status. Refer to the description of

the DYN_OUT bit in Section 15.5.9.

EP2FIFOCFG

see Section 15.14

Endpoint 2/Slave FIFO Configuration E618

EP4FIFOCFG

see Section 15.14

Endpoint 4/Slave FIFO Configuration E619

EP6FIFOCFG

see Section 15.14

Endpoint 6/Slave FIFO Configuration E61A

EP8FIFOCFG

see Section 15.14

Endpoint 8/Slave FIFO Configuration E61B

b7 b6 b5 b4 b3 b2 b1 b0

0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE

R R/W R/W R/W R/W R/W R R/W

0 0 0 0 0 1 0 1

1 2 ... 344 345 346 347 348 349 350 351 352 353 354 ... 459 460

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Cypress Semiconductor FX2LP Informations techniques Page 349