Cypress Semiconductor FX2LP Informations techniques télécharger pdf (Page 217)

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Chapter 10. General Programmable Interface (GPIF) Page 10-27

TD_Init():

… … … … …

GpifInit(); // Configures GPIF from GPIFTool generated waveform data

// TODO: configure other endpoints, etc. here

// TODO: arm OUT buffer(s) here

// setup INT4 as internal source for GPIF interrupts

// using INT4CLR (SFR), automatically enabled

//INTSETUP |= 0x03; //Enable INT4 Autovectoring

// SYNCDELAY;

//GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupt(s)

// SYNCDELAY;

//EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4)=1

// TODO: configure GPIF interrupt(s) to meet your needs here

… … … … …

void GpifInit( void )

{

BYTE i;

// Registers which require a synchronization delay, see section 15.14

// FIFORESET FIFOPINPOLAR

// INPKTEND OUTPKTEND

// EPxBCH:L REVCTL

// GPIFTCB3 GPIFTCB2

// GPIFTCB1 GPIFTCB0

// EPxFIFOPFH:L EPxAUTOINLENH:L

// EPxFIFOCFG EPxGPIFFLGSEL

// PINFLAGSxx EPxFIFOIRQ

// EPxFIFOIE GPIFIRQ

// GPIFIE GPIFADRH:L

// UDMACRCH:L EPxGPIFTRIG

// GPIFTRIG

// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...

// ...these have been replaced by GPIFTC[B3:B0] registers

// 8051 doesn't have access to waveform memories 'til

// the part is in GPIF mode.

IFCONFIG = 0xCE;

// IFCLKSRC=1 , FIFOs executes on internal clk source

// xMHz=1 , 48MHz internal clk rate

// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz

// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk

// ASYNC=1 , master samples asynchronous

// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF

// IFCFG[1:0]=10, FX2 in GPIF master mode

GPIFABORT = 0xFF; // abort any waveforms pending

GPIFREADYCFG = InitData[ 0 ];

GPIFCTLCFG = InitData[ 1 ];

GPIFIDLECS = InitData[ 2 ];

GPIFIDLECTL = InitData[ 3 ];

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Cypress Semiconductor FX2LP Informations techniques Page 217

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