Cypress Semiconductor FX2LP Informations techniques télécharger pdf (Page 289)

Chapter 13. Input/Output Page 13-15

While the I²C-Compatible Bus controller is generating the “stop” condition, it ignores accesses to

the I2CS and I2DAT registers. Firmware should therefore check the STOP Bit for zero before writ-

ing new data to I2CS or I2DAT.

An interrupt request is available to signal that the STOP condition is complete.

LASTRD

The master reads data by floating the SDA line and issuing clock pulses on the SCL line; after

every eight bits, it drives SDA low for one clock to indicate ACK. To signal the last byte of a multi-

byte transfer, the master floats SDA at ACK time to instruct the slave to stop sending.

When LASTRD = 1, the FX2 will float the SDA line after the next read transfer. The LASTRD bit is

automatically cleared at the end of the transfer (at ACK time).

Setting LASTRD does not automatically generate a STOP condition. At the end of a read transfer,

the STOP bit should also be set.

13.4.2.2 Status Bits

After a byte transfer, the FX2 updates the three status bits DONE, ACK, and BERR. If no STOP

condition was transmitted, they are updated at ACK time; if a STOP condition was transmitted,

they are updated after the STOP.

DONE

The FX2 sets this bit whenever it completes a byte transfer. The FX2 also generates an interrupt

request when it sets the DONE bit. The DONE bit is automatically cleared when the I2DAT register

is read or written, and the interrupt request bit is automatically cleared whenever the I2CS or

I2DAT registers are read or written.

ACK

Every ninth SCL of a write transfer, the slave indicates reception of the byte by asserting ACK. The

FX2 floats SDA during this time, samples the SDA line, and updates the ACK bit with the comple-

ment of the detected value. ACK=1 indicates acknowledge, and ACK=0 indicates not-acknowl-

edge. The ACK bit should be ignored for read transfers on the bus.

BERR

This bit indicates a bus error. BERR=1 indicates that there was bus contention, which results when

an outside device drives the bus when it shouldn’t, or when another bus master wins arbitration

and takes control of the bus. When a bus error is detected, the current transfer is immediately can-

celled, the FX2 floats the SCL and SDA lines, and the bus controller is disabled until a STOP con-

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Cypress Semiconductor FX2LP Informations techniques Page 289