Cypress Semiconductor FX2LP Informations techniques télécharger pdf (Page 134)

EZ-USB FX2 Technical Reference Manual

Page 7-4 EZ-USB FX2 Technical Reference Manual v2.1

• No “C0/C2” EEPROM is detected on the I²C-compatible bus.

Under these conditions, the FX2 also sets the RENUM bit to 1, so the firmware will be responsible

for responding to USB device requests.

7.4 CPU Reset Effects

The USB host may reset the CPU at any time by downloading the value 0x01 to the CPUCS regis-

ter. The host might do this, for example, in preparation for loading code overlays, effectively mag-

nifying the size of the internal FX2 RAM. For such applications, it is important to know the state of

the FX2 chip during and after a CPU reset. In this section, this particular reset is called a “CPU

Reset,” and should not be confused with the POR described in Section 7.2,

"Power-On Reset

(POR)."

This discussion applies only to the condition in which the FX2 chip is powered, and the

CPU is reset by the host setting the CPUCS.0 bit to 1.

The basic USB device configuration remains intact through a CPU reset. Endpoints keep their

configuration, the USB Function Address remains the same, and the I/O ports retain their configu-

rations and values. Stalled endpoints remain stalled, data toggles don’t change, and the RENUM

bit is unaffected. The only effects of a CPU reset are as follows:

• USB (INT2) interrupts are disabled, but pending interrupt requests remain pending.

• When the CPU comes out of reset, pending interrupts are kept pending, but disabled. This

gives the firmware writer the choice of acting on pre-reset USB events, or ignoring them

by clearing the pending interrupt(s) before enabling INT2.

• The breakpoint condition (BREAKPT.3) is cleared.

• While the CPU is in reset, the FX2 will enter the Suspend state automatically if a “sus-

pend” condition is detected on the bus.

7.5 USB Bus Reset

The host signals a USB Bus Reset by driving an SE0 state (both D+ and D- data lines low) for a

minimum of 10 ms. The FX2 senses this condition, requests the USB Interrupt (INT2), and sup-

plies the interrupt vector for a USB Reset. After a USB bus reset, the following occurs:

• Toggle bits are cleared to 0.

• The device address is reset to zero.

• If the Default USB Device is active, the USB configuration and alternate settings are reset

to zero.

• The FX2 will renegotiate with the host for high-speed (480 Mbps) mode.

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Cypress Semiconductor FX2LP Informations techniques Page 134