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Chapter 12. Instruction Set Page 12-1

Chapter 12 Instruction Set

12.1 Introduction

This chapter provides a technical overview and description of the FX2’s assembly-language

instruction set.

All FX2 instructions are binary-code-compatible with the standard 8051. The FX2 instructions

affect bits, flags, and other status functions just as the 8051 instructions do. Instruction timing,

however, is different both in terms of the number of clock cycles per instruction cycle and the num-

ber of instruction cycles used by each instruction.

Table 12-2 lists the FX2 instruction set and the number of instruction cycles required to complete

each instruction. Table 12-1 defines the symbols and mnemonics used in Table 12-2.

Table 12-1. Legend for Instruction Set Table

Symbol Function

A Accumulator

Rn Register (R0–R7, in the bank selected by RS1:RS0)

direct Internal RAM location (0x00 - 0x7F in the “Lower 128”, or 0x80 - 0xFF in “SFR” space)

@Ri Internal RAM location (0x00 - 0x7F in the “Lower 128”, or 0x80 - 0xFF in the “Upper 128”)

pointed to by R0 or R1

rel Program-memory offset (-128 to +127 bytes relative to the first byte of the following

instruction). Used by conditional jumps and SJMP.

bit Bit address (0x20 - x2F in the “Lower 128,” and SFRs 0x80, 0x88, ...., 0xF0, 0xF8)

#data 8-bit constant (0 - 255)

#data16 16-bit constant (0 - 65535)

addr16 16-bit destination address; used by LCALL and LJMP, which branch anywhere in program

memory

addr11 11-bit destination address; used by ACALL and AJMP, which branch only within the cur-

rent 2K page of program memory (i.e., the upper 5 address bits are copied from the PC)

PC Program Counter; holds the address of the currently-executing instruction. For the pur-

poses of “ACALL”, “AJMP”, and “MOVC A,@A+PC” instructions, the PC holds the

address of the first byte of the instruction following the currently-executing instruction.

1 2 ... 262 263 264 265 266 267 268 269 270 271 272 ... 459 460

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Cypress Semiconductor FX2LP Informations techniques Page 267