Cypress Semiconductor FX2LP Informations techniques télécharger pdf (Page 171)

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Chapter 9. Slave FIFOs Page 9-15

9.2.9 Implementing Asynchronous Slave FIFO Writes

Figure 9-19. Interface Pins Example: Asynchronous FIFO Writes

Typically, the sequence of events for the external master is:

IDLE: When write event occurs, transition to State 1.

STATE 1: Point to IN FIFO, assert FIFOADR[1:0], transition to State 2.

STATE 2: If FIFO-Full flag is false (FIFO not full), transition to State 3 else remain in State 2.

STATE 3: Drive data on the bus, increment pointer by asserting then de-asserting SLWR, transition

to State 4.

STATE 4: If more data to write, transition to State 2 else transition to IDLE.

Figure 9-20. State Machine Example: Asynchronous FIFO Writes

FLAGB

FLAGC

SLWR

PKTEND

FIFOADR[1:0]

FD[15:0]

FX2

Slave

Mode

EXT.

Master

FULL

EMPTY

State 3

State 2

State 4

Done

Launch

Full

State 1

1 2 ... 166 167 168 169 170 171 172 173 174 175 176 ... 459 460

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